📄 ds1302driver_io.lst
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Sunplus u'nSP Assembler - Ver. 1.14.3.1
Listing File Has Been Relocated
//======================================================
// 文件名称： DS1302Driver_IO.asm
// 功能描述： DS1302底层驱动程序，主要是与时序有关的代码
// 维护记录： 2006-06-14 v1.0
// Mz出品 时序经典
// 注 意： 汇编语言版
//======================================================
// IO port control registers
.DEFINE P_IOA_Data 0x7000
.DEFINE P_IOA_Buffer 0x7001
.DEFINE P_IOA_Dir 0x7002
.DEFINE P_IOA_Attrib 0x7003
.DEFINE P_IOA_Latch 0x7004
.DEFINE P_IOB_Data 0x7005
.DEFINE P_IOB_Buffer 0x7006
.DEFINE P_IOB_Dir 0x7007
.DEFINE P_IOB_Attrib 0x7008
//redefine the I/O port for DS1302
.DEFINE Port_Data P_IOB_Data
.DEFINE Port_Buffer P_IOB_Buffer
.DEFINE Port_Dir P_IOB_Dir
.DEFINE Port_Attrib P_IOB_Attrib
//Define the I/O Port bit connected with DS1302, just as CE\DA\CLK
.DEFINE M_CE 0x8000
.DEFINE M_DA 0x4000
.DEFINE M_CLK 0x2000
00009768 .CODE
//======================================================
// 汇编格式： _F_DS1302_Initial_IO
// C格式： void F_DS1302_Initial_IO(void);
// 实现功能： 端口初始化子程序
// 入口参数： 无
// 出口参数： 无
//======================================================
.PUBLIC _F_DS1302_Initial_IO
_F_DS1302_Initial_IO:
00009768 11 93 07 70 r1 = [Port_Dir]
0000976A 09 A3 00 E0 r1 = r1|(M_CE+M_DA+M_CLK)
0000976C 19 D3 07 70 [Port_Dir] = r1
0000976E 11 93 08 70 r1 = [Port_Attrib]
00009770 09 A3 00 E0 r1 = r1|(M_CE+M_DA+M_CLK)
00009772 19 D3 08 70 [Port_Attrib] = r1
00009774 11 93 06 70 r1 = [Port_Buffer]
00009776 09 B3 FF 1F r1 = r1&(~(M_CE+M_DA+M_CLK))
00009778 19 D3 06 70 [Port_Buffer] = r1
0000977A 11 93 05 70 r1 = [Port_Data]
0000977C 09 A3 00 E0 r1 = r1|(M_CE+M_DA+M_CLK)
0000977E 19 D3 08 70 [Port_Attrib] = r1
00009780 90 9A retf
//======================================================
// 汇编格式： _F_DS1302_WriteByte
// C格式： void F_DS1302_WriteByte(unsigned int Addr,unsigned int Data)
// 实现功能： 写一个字节数据至DS1302的指定地址的空间当中
// 入口参数： Addr 指定的地址
// Data 要写入的数据
// 出口参数： 无
//======================================================
.PUBLIC _F_DS1302_WriteByte
_F_DS1302_WriteByte:
00009781 88 DA push bp to [sp]
00009782 08 0B 04 00 bp = sp+4
00009784 C5 92 r1 = [bp] //get Addr
00009785 09 B3 FF 00 r1 = r1&0x00ff
00009787 01 94 r2 = [bp+1] //Get Data
00009788 5A 95 r2 = r2 lsl 4
00009789 5A 03 r1 =r1+r2 lsl 4 //
0000978A 50 98 r4 = 16
0000978B 12 95 06 70 r2 = [Port_Buffer]
0000978D 0A A5 00 80 r2 = r2|M_CE
0000978F 1A D5 06 70 [Port_Buffer] = r2 //CE to hight ??
?Write_Loop:
00009791 41 C2 test r1,0x0001
00009792 03 5E jz ?Write_0
00009793 0A A5 00 40 r2 = r2|M_DA
00009795 02 EE jmp ?Write_DD
?Write_0:
00009796 0A B5 FF BF r2 = r2&(~M_DA)
?Write_DD:
00009798 1A D5 06 70 [Port_Buffer] = r2 //Send Data to the I/O
0000979A 0A A7 00 20 r3 = r2|M_CLK
0000979C 1B D7 06 70 [Port_Buffer] = r3 //CLK to Hight
0000979E 61 93 r1 = r1 lsr 1
0000979F 41 28 r4-=1
000097A0 03 5E jz ?Write_Exit
000097A1 1A D5 06 70 [Port_Buffer] = r2 //CLK to Low
000097A3 53 EE jmp ?Write_Loop
?Write_Exit:
000097A4 1A D5 06 70 [Port_Buffer] = r2
000097A6 0A B5 FF 3F r2 = r2&(~(M_DA+M_CE))
000097A8 1A D5 06 70 [Port_Buffer] = r2
000097AA 88 98 pop bp from [sp]
000097AB 90 9A retf
//======================================================
// 汇编格式： _F_DS1302_ReadByte
// C格式： unsigned int F_DS1302_ReadByte(unsigned int Addr)
// 实现功能： 计取DS1302当中指写地址空间的一个字节数据数据
// 入口参数： Addr 指定的地址
// 出口参数： 无
//======================================================
.PUBLIC _F_DS1302_ReadByte
_F_DS1302_ReadByte:
000097AC 88 DA push r5 to [sp]
000097AD 48 98 r4 = 8
000097AE 12 95 06 70 r2 = [Port_Buffer]
000097B0 0A A5 00 80 r2 = r2|M_CE
000097B2 1A D5 06 70 [Port_Buffer] = r2 //CE to hight ??
?Write1_Loop:
000097B4 41 C2 test r1,0x0001
000097B5 03 5E jz ?Write1_0
000097B6 0A A5 00 40 r2 = r2|M_DA
000097B8 02 EE jmp ?Write1_DD
?Write1_0:
000097B9 0A B5 FF BF r2 = r2&(~M_DA)
?Write1_DD:
000097BB 1A D5 06 70 [Port_Buffer] = r2 //Send Data to the I/O
000097BD 0A A7 00 20 r3 = r2|M_CLK
000097BF 1B D7 06 70 [Port_Buffer] = r3 //CLK to Hight
000097C1 61 93 r1 = r1 lsr 1
000097C2 41 28 r4-=1
000097C3 03 5E jz ?Read_DD
000097C4 1A D5 06 70 [Port_Buffer] = r2 //CLK to Low
000097C6 53 EE jmp ?Write1_Loop
?Read_DD:
000097C7 11 93 07 70 r1 = [Port_Dir]
000097C9 09 B3 FF BF r1 = r1&(~M_DA)
000097CB 19 D3 07 70 [Port_Dir] = r1 //I/O as Floating input
000097CD 40 92 r1 = 0 //Clear r1
000097CE 48 98 r4 = 8
000097CF 0A A7 00 20 r3 = r2|M_CLK //R3 save the status as CLK is Hight
?Read_Loop:
000097D1 1A D5 06 70 [Port_Buffer] = r2 //CLK to low
000097D3 61 93 r1 = r1 lsr 1
000097D4 00 EE nop //for clk data delay,if cpuclock is highter,user shoud insert more 'nop'
000097D5 15 9B 05 70 r5 = [Port_Data] //Read the data of DS1302`s data port
000097D7 0D BB 00 40 r5 = r5&M_DA
000097D9 02 5E jz ?Read_0
000097DA 0D 9B 80 00 r5 = 0x0080 //lsb first so......
?Read_0:
000097DC 05 A3 r1 = r1|r5
000097DD 1B D7 06 70 [Port_Buffer] = r3 //CLK to hight
000097DF 41 28 r4-=1
000097E0 50 4E jnz ?Read_Loop
000097E1 13 97 07 70 r3 = [Port_Dir]
000097E3 0B A7 00 40 r3 = r3|M_DA
000097E5 1B D7 07 70 [Port_Dir] = r3 //I/O as Output port
000097E7 0A B5 FF 5F r2 = r2&(~(M_CE+M_CLK))
000097E9 1A D5 06 70 [Port_Buffer] = r2 //Set the CLK\CE to Low
000097EB 88 98 pop r5 from [sp]
000097EC 90 9A retf
0 error(s), 0 warning(s).
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