ruan.txt

扩频发射机

附录:
1.时钟模块
module clock(clk32_64M,clk16_32M,clk2_04M,clk8k,clk4k);
  input clk32_64M;
  output clk16_32M,clk2_04M,clk8k,clk4k;
  reg clk16_32M,clk2_04M,clk8k,clk4k;
  reg[2:0] count2;
  reg[10:0] count3;
  reg[11:0] count4;
  initial
    begin
      count2=3'b000;
      count3=11'b00000000000;
      count4=12'b000000000000;
    end
  always @(posedge clk32_64M)
    clk16_32M=~clk16_32M;
  always @(posedge clk32_64M)
    begin
      if(count2==3'b111)begin count2=0;clk2_04M=~clk2_04M;end
      else begin count2=count2+1;end
    end
  always @(posedge clk32_64M)
    begin
      if(count3==11'b11111110111)begin count3=0;clk8k=~clk8k;end
      else begin count3=count3+1;end
    end
  always @(posedge clk32_64M)
    begin
      if(count4==12'b111111101111)begin count4=0;clk4k=~clk4k;end
      else begin count4=count4+1;end
    end
endmodule

2.rom模块
module rom(s,clk4k,reset);
  input clk4k,reset;
  output s;
  reg s;
  reg[7:0] addr;
  always @(posedge clk4k)
    begin
      if(!reset)
        addr=0;
      else 
        begin
          if(addr==200)
            begin
              addr=0;
              s=0;
            end
          else
            begin
            case(addr)
            0:s=0;1:s=0;2:s=1;3:s=1;4:s=0;
            5:s=1;6:s=1;7:s=0;8:s=1;9:s=1;
            10:s=0;11:s=0;12:s=1;13:s=1;14:s=0;
            15:s=1;16:s=0;17:s=1;18:s=1;19:s=1;
            20:s=0;21:s=0;22:s=1;23:s=1;24:s=0;
            25:s=1;26:s=0;27:s=0;28:s=1;29:s=1;
            30:s=0;31:s=0;32:s=1;33:s=1;34:s=0;
            35:s=1;36:s=1;37:s=1;38:s=1;39:s=1;
            40:s=0;41:s=0;42:s=1;43:s=1;44:s=0;
            45:s=1;46:s=1;47:s=1;48:s=1;49:s=1;
            50:s=0;51:s=0;52:s=1;53:s=1;54:s=0;
            55:s=1;56:s=1;57:s=1;58:s=1;59:s=1;
            60:s=0;61:s=0;62:s=1;63:s=1;64:s=0;
            65:s=1;66:s=1;67:s=1;68:s=1;69:s=1;
            70:s=0;71:s=0;72:s=1;73:s=1;74:s=0;
            75:s=1;76:s=1;77:s=1;78:s=1;79:s=1;
            80:s=0;81:s=0;82:s=1;83:s=1;84:s=0;
            85:s=1;86:s=1;87:s=1;88:s=1;89:s=1;
            90:s=0;91:s=0;92:s=1;93:s=1;94:s=0;
            95:s=1;96:s=1;97:s=1;98:s=1;99:s=1;
            100:s=0;101:s=0;102:s=1;103:s=1;104:s=0;
            105:s=1;106:s=1;107:s=1;108:s=1;109:s=1;
            110:s=0;111:s=0;112:s=1;113:s=1;114:s=0;
            115:s=1;116:s=1;117:s=1;118:s=1;119:s=1;
            120:s=0;121:s=0;122:s=1;123:s=1;124:s=0;
            125:s=1;126:s=1;127:s=1;128:s=1;129:s=1;
            130:s=0;131:s=0;132:s=1;133:s=1;134:s=0;
            135:s=1;136:s=1;137:s=1;138:s=1;139:s=1;
            140:s=0;141:s=0;142:s=1;143:s=1;144:s=0;
            145:s=1;146:s=1;147:s=1;148:s=1;149:s=1;
            150:s=0;151:s=0;152:s=1;153:s=1;154:s=0;
            155:s=1;156:s=1;157:s=1;158:s=1;159:s=1;
            160:s=0;161:s=0;162:s=1;163:s=1;164:s=0;
            165:s=1;166:s=1;167:s=1;168:s=1;169:s=1;
            170:s=0;171:s=0;172:s=1;173:s=1;174:s=0;
            175:s=1;176:s=1;177:s=1;178:s=1;179:s=1;
            180:s=0;181:s=0;182:s=1;183:s=1;184:s=0;
            185:s=1;186:s=1;187:s=1;188:s=1;189:s=1;
            190:s=0;191:s=0;192:s=1;193:s=1;194:s=0;
            195:s=0;196:s=0;197:s=0;198:s=0;199:s=0;
            default:s=0;                                                                     
            endcase
            end
        end
        addr=addr+1;
     end
endmodule

3.卷积模块
module convolute(out,in,clk8k,reset);
  input in,clk8k,reset;
  output out;
  reg out,out1,out0,count;
  reg[6:0] tem;
  always @(negedge clk8k)
    begin
      if(!reset)
        begin
          tem=0;
          count=0;
        end
      else if(count==0)
        begin
          count=~count;
          tem[6]=tem[5];
          tem[5]=tem[4];
          tem[4]=tem[3];
          tem[3]=tem[2];
          tem[2]=tem[1];
          tem[1]=tem[0];
          tem[0]=in;
          out1=tem[0]+tem[2]+tem[3]+tem[5]+tem[6];
          out0=tem[0]+tem[1]+tem[2]+tem[3]+tem[6];
          out=out0;
        end
      else
        begin
          count=~count;
          out=out1;
        end
    end  
endmodule

4.扩频模块
module kuopin(out,clk2_04M,reset,in);
  input in,clk2_04M,reset;
  output out;
  reg out,in_data,tem;
  reg[7:0] count;
  reg[3:0] kasami1;
  reg[7:0] kasami2;
  always @(posedge clk2_04M)
    begin
      if(!reset)
        begin
          count<='b00000000; 
          in_data<=0;
          tem<=0;
          kasami1<=4'b0101;
          kasami2<=8'b10100101;
        end
      else
        begin
          count<=count+1;
          out<=!(kasami1[0]^kasami2[0]^in_data);
          kasami1<=kasami1>>1;
          kasami2<=kasami2>>1;
          kasami1[3]<=kasami1[0]^kasami1[1];
          kasami2[7]<=kasami2[0]^kasami2[2]^kasami2[3]^kasami2[4];
          if(count=='b01111111)
            begin
              tem<=in;
            end
          else if(count=='b11111111)
            begin
              count<='b00000000;
              in_data<=tem;
            end
        end
    end
endmodule

5.极性变换和内插模块
module jixingbianhuan(out,in,clk16_32M);
  input clk16_32M,in;
  output[2:0] out;
  reg[2:0] count;
  reg[2:0] out;
  initial 
     begin
       count='b000;
     end
  always @(negedge clk16_32M)
    begin
      if(count=='b000)
        begin
          out<=(in==1)?'b111:'b001;
        end
      else if(count=='b111)
        begin
          out<='b000;
          count<='b000;
        end
      else
        out<='b000;
      count<=count+1;
    end
endmodule 

6.顶层模块
module main(clk32_64M,reset,dataout);
  input reset,clk32_64M;
  output[2:0] dataout;
  reg w16_32M,w2_04M,w8k,w4k;
  reg s1,s2,s3;
  reg[2:0] dataout;
  clock  u1(clk32_64M,w16_32M,w2_04M,w8k,w4k);
  rom   u2(s1,w4k,reset);
  convolute u3(s2,s1,w8k,reset);
  kuopin  u4(s3,w2_04M,reset,s2);
  jixingbianhuan u5(dataout,s3,w16_32M);
endmodule