dwc_otg_cil_intr.c

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		dwc_otg_core_init(_core_if);
		dwc_otg_enable_global_interrupts(_core_if);
		pcd_start(_core_if);
	} else {
		/* A-Device connector (Host Mode) */
		while (!dwc_otg_is_host_mode(_core_if)) {
			printk("Waiting for Host Mode, Mode=%s\n",
				  (dwc_otg_is_host_mode(_core_if) ? "Host" : "Peripheral"));
			mdelay(100);
			if (++count > 10000)
				*(uint32_t *) NULL = 0;
		}
		_core_if->op_state = A_HOST;
		/*
		 * Initialize the Core for Host mode.
		 */
		dwc_otg_core_init(_core_if);
		dwc_otg_enable_global_interrupts(_core_if);
		hcd_start(_core_if);
	}

	/* Set flag and clear interrupt */
	gintsts.b.conidstschng = 1;
	dwc_write_reg32(&_core_if->core_global_regs->gintsts, gintsts.d32);

	return 1;
}

/**
 * This interrupt indicates that a device is initiating the Session
 * Request Protocol to request the host to turn on bus power so a new
 * session can begin. The handler responds by turning on bus power. If
 * the DWC_otg controller is in low power mode, the handler brings the
 * controller out of low power mode before turning on bus power.
 *
 * @param _core_if Programming view of DWC_otg controller.
 */
int32_t dwc_otg_handle_session_req_intr (dwc_otg_core_if_t * _core_if)
{
#ifndef DWC_HOST_ONLY
	hprt0_data_t hprt0;
#endif
	gintsts_data_t gintsts;

#ifndef DWC_HOST_ONLY
	DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");

	if (dwc_otg_is_device_mode(_core_if)) {
		DWC_PRINT("SRP: Device mode\n");
	} else {
		DWC_PRINT("SRP: Host mode\n");

		/* Turn on the port power bit. */
		hprt0.d32 = dwc_otg_read_hprt0(_core_if);
		hprt0.b.prtpwr = 1;
		dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);

		/* Start the Connection timer. So a message can be displayed
		 * if connect does not occur within 10 seconds. */
		hcd_session_start(_core_if);
	}
#endif

	/* Clear interrupt */
	gintsts.d32 = 0;
	gintsts.b.sessreqintr = 1;
	dwc_write_reg32(&_core_if->core_global_regs->gintsts, gintsts.d32);

	return 1;
}

/**
 * This interrupt indicates that the DWC_otg controller has detected a
 * resume or remote wakeup sequence. If the DWC_otg controller is in
 * low power mode, the handler must brings the controller out of low
 * power mode. The controller automatically begins resume
 * signaling. The handler schedules a time to stop resume signaling.
 */
int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * _core_if)
{
	gintsts_data_t gintsts;

	DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n");

	if (dwc_otg_is_device_mode(_core_if)) {
		dctl_data_t dctl = {.d32 = 0 };
		DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
			    dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dsts));
#ifdef PARTIAL_POWER_DOWN
		if (_core_if->hwcfg4.b.power_optimiz) {
			pcgcctl_data_t power = {.d32 = 0 };

			power.d32 = dwc_read_reg32(_core_if->pcgcctl);
			DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32);

			power.b.stoppclk = 0;
			dwc_write_reg32(_core_if->pcgcctl, power.d32);

			power.b.pwrclmp = 0;
			dwc_write_reg32(_core_if->pcgcctl, power.d32);

			power.b.rstpdwnmodule = 0;
			dwc_write_reg32(_core_if->pcgcctl, power.d32);
		}
#endif
		/* Clear the Remote Wakeup Signalling */
		dctl.b.rmtwkupsig = 1;
		dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);

		if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup) {
			_core_if->pcd_cb->resume_wakeup(_core_if->pcd_cb->p);
		}

	} else {
		/*
		 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
		 * so that OPT tests pass with all PHYs).
		 */
		hprt0_data_t hprt0 = {.d32 = 0 };
		pcgcctl_data_t pcgcctl = {.d32 = 0 };
		/* Restart the Phy Clock */
		pcgcctl.b.stoppclk = 1;
		dwc_modify_reg32(_core_if->pcgcctl, pcgcctl.d32, 0);
		udelay(10);

		/* Now wait for 70 ms. */
		hprt0.d32 = dwc_otg_read_hprt0(_core_if);
		printk("Resume: HPRT0=%0x\n", hprt0.d32);
		mdelay(70);
		hprt0.b.prtres = 0;	/* Resume */
		dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32);
		DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
			    dwc_read_reg32(_core_if->host_if->hprt0));
	}

	/* Clear interrupt */
	gintsts.d32 = 0;
	gintsts.b.wkupintr = 1;
	dwc_write_reg32(&_core_if->core_global_regs->gintsts, gintsts.d32);

	return 1;
}

/**
 * This interrupt indicates that a device has been disconnected from
 * the root port.
 */
int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * _core_if)
{
	gintsts_data_t gintsts;

	DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
		    (dwc_otg_is_host_mode(_core_if) ? "Host" : "Device"), op_state_str(_core_if));

/** @todo Consolidate this if statement. */
#ifndef DWC_HOST_ONLY
	if (_core_if->op_state == B_HOST) {
		/* If in device mode Disconnect and stop the HCD, then
		 * start the PCD. */
		hcd_disconnect(_core_if);
		pcd_start(_core_if);
		_core_if->op_state = B_PERIPHERAL;
	} else if (dwc_otg_is_device_mode(_core_if)) {
		gotgctl_data_t gotgctl = {.d32 = 0 };
		gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl);
		if (gotgctl.b.hstsethnpen == 1) {
			/* Do nothing, if HNP in process the OTG
			 * interrupt "Host Negotiation Detected"
			 * interrupt will do the mode switch.
			 */
		} else if (gotgctl.b.devhnpen == 0) {
			/* If in device mode Disconnect and stop the HCD, then
			 * start the PCD. */
			hcd_disconnect(_core_if);
			pcd_start(_core_if);
			_core_if->op_state = B_PERIPHERAL;
		} else {
			DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
		}
	} else {
		if (_core_if->op_state == A_HOST) {
			/* A-Cable still connected but device disconnected. */
			hcd_disconnect(_core_if);
		}
	}
#endif

	gintsts.d32 = 0;
	gintsts.b.disconnect = 1;
	dwc_write_reg32(&_core_if->core_global_regs->gintsts, gintsts.d32);
	return 1;
}

/**
 * This interrupt indicates that SUSPEND state has been detected on
 * the USB.
 *
 * For HNP the USB Suspend interrupt signals the change from
 * "a_peripheral" to "a_host".
 *
 * When power management is enabled the core will be put in low power
 * mode.
 */
int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * _core_if)
{
	dsts_data_t dsts;
	gintsts_data_t gintsts;

	DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");

	if (dwc_otg_is_device_mode(_core_if)) {
		/* Check the Device status register to determine if the Suspend
		 * state is active. */
		dsts.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dsts);
		DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
		DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
			    "HWCFG4.power Optimize=%d\n",
			    dsts.b.suspsts, _core_if->hwcfg4.b.power_optimiz);


#ifdef PARTIAL_POWER_DOWN
/** @todo Add a module parameter for power management. */

		if (dsts.b.suspsts && _core_if->hwcfg4.b.power_optimiz) {
			pcgcctl_data_t power = {.d32 = 0 };
			DWC_DEBUGPL(DBG_CIL, "suspend\n");

			power.b.pwrclmp = 1;
			dwc_write_reg32(_core_if->pcgcctl, power.d32);

			power.b.rstpdwnmodule = 1;
			dwc_modify_reg32(_core_if->pcgcctl, 0, power.d32);

			power.b.stoppclk = 1;
			dwc_modify_reg32(_core_if->pcgcctl, 0, power.d32);

		} else {
			DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
		}
#endif
		/* PCD callback for suspend. */
		pcd_suspend(_core_if);
	} else {
		if (_core_if->op_state == A_PERIPHERAL) {
			DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
			/* Clear the a_peripheral flag, back to a_host. */
			pcd_stop(_core_if);
			hcd_start(_core_if);
			_core_if->op_state = A_HOST;
		}
	}

	/* Clear interrupt */
	gintsts.d32 = 0;
	gintsts.b.usbsuspend = 1;
	dwc_write_reg32(&_core_if->core_global_regs->gintsts, gintsts.d32);

	return 1;
}

#define DWC_INT_MSK_COMMON 0xf1000806

/**
 * This function returns the Core Interrupt register.
 */
static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * _core_if)
{
#if 0
	gintsts_data_t gintsts;
	gintmsk_data_t gintmsk;

	gintmsk_data_t gintmsk_common = {.d32 = 0 };
	gintmsk_common.b.wkupintr = 1;
	gintmsk_common.b.sessreqintr = 1;
	gintmsk_common.b.conidstschng = 1;
	gintmsk_common.b.otgintr = 1;
	gintmsk_common.b.modemismatch = 1;
	gintmsk_common.b.disconnect = 1;
	gintmsk_common.b.usbsuspend = 1;
	/** @todo: The port interrupt occurs while in device
         * mode. Added code to CIL to clear the interrupt for now!
         */
	gintmsk_common.b.portintr = 1;

	printk("gintmsk_common.d32: %08x\n", gintmsk_common.d32);

	gintsts.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintsts);
	gintmsk.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintmsk);
#ifdef DEBUG
	/* if any common interrupts set */
	if (gintsts.d32 & gintmsk_common.d32) {
		DWC_DEBUGPL(DBG_ANY, "gintsts=%08x  gintmsk=%08x\n", gintsts.d32, gintmsk.d32);
	}
#endif

	return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
#else
	u32 sts, msk;

	sts = readl(S3C_UDC_OTG_GINTSTS);
	msk = readl(S3C_UDC_OTG_GINTMSK);

	return ((sts & msk) & DWC_INT_MSK_COMMON);
#endif
}

/**
 * Common interrupt handler.
 *
 * The common interrupts are those that occur in both Host and Device mode.
 * This handler handles the following interrupts:
 * - Mode Mismatch Interrupt
 * - Disconnect Interrupt
 * - OTG Interrupt
 * - Connector ID Status Change Interrupt
 * - Session Request Interrupt.
 * - Resume / Remote Wakeup Detected Interrupt.
 *
 */
extern int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * _core_if, uint sts)
{
	int retval = IRQ_NONE;
	gintsts_data_t gintsts;

	gintsts.d32 = sts;

	if (gintsts.b.modemismatch) {
		retval |= dwc_otg_handle_mode_mismatch_intr(_core_if);
	}
	if (gintsts.b.otgintr) {
		retval |= dwc_otg_handle_otg_intr(_core_if);
	}
	if (gintsts.b.conidstschng) {
		retval |= dwc_otg_handle_conn_id_status_change_intr(_core_if);
	}
	if (gintsts.b.disconnect) {
		retval |= dwc_otg_handle_disconnect_intr(_core_if);
	}
	if (gintsts.b.sessreqintr) {
		retval |= dwc_otg_handle_session_req_intr(_core_if);
	}
	if (gintsts.b.wkupintr) {
		retval |= dwc_otg_handle_wakeup_detected_intr(_core_if);
	}
	if (gintsts.b.usbsuspend) {
		retval |= dwc_otg_handle_usb_suspend_intr(_core_if);
	}
	if (gintsts.b.portintr && dwc_otg_is_device_mode(_core_if)) {
		/* The port interrupt occurs while in device mode with HPRT0
		 * Port Enable/Disable.
		 */
		gintsts.d32 = 0;
		gintsts.b.portintr = 1;
		dwc_write_reg32(&_core_if->core_global_regs->gintsts, gintsts.d32);
		retval |= 1;

	}
	return retval;
}