dwc_otg_regs.h

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#define DWC_STS_DATA_UPDT		0x2	// OUT Data Packet
#define DWC_STS_XFER_COMP		0x3	// OUT Data Transfer Complete

#define DWC_DSTS_GOUT_NAK		0x1	// Global OUT NAK
#define DWC_DSTS_SETUP_COMP		0x4	// Setup Phase Complete
#define DWC_DSTS_SETUP_UPDT 0x6	// SETUP Packet
		unsigned pktsts:4;
		unsigned fn:4;
		unsigned reserved:7;
	} b;
} device_grxsts_data_t;

/**
 * This union represents the bit fields in the Host Receive Status Read and
 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
 * element then read out the bits using the <i>b</i>it elements.
 */
typedef union host_grxsts_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		unsigned chnum:4;
		unsigned bcnt:11;
		unsigned dpid:2;

		unsigned pktsts:4;
#define DWC_GRXSTS_PKTSTS_IN			  0x2
#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP	  0x3
#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
#define DWC_GRXSTS_PKTSTS_CH_HALTED		  0x7

		unsigned reserved:11;
	} b;
} host_grxsts_data_t;

/**
 * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
 * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element then
 * read out the bits using the <i>b</i>it elements.
 */
typedef union fifosize_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		unsigned startaddr:16;
		unsigned depth:16;
	} b;
} fifosize_data_t;

/**
 * This union represents the bit fields in the Non-Periodic Transmit
 * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
 * <i>d32</i> element then read out the bits using the <i>b</i>it
 * elements.
 */
typedef union gnptxsts_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		unsigned nptxfspcavail:16;
		unsigned nptxqspcavail:8;
		/** Top of the Non-Periodic Transmit Request Queue
		 *	- bit 24 - Terminate (Last entry for the selected
		 *	  channel/EP)
		 *	- bits 26:25 - Token Type
		 *	  - 2'b00 - IN/OUT
		 *	  - 2'b01 - Zero Length OUT
		 *	  - 2'b10 - PING/Complete Split
		 *	  - 2'b11 - Channel Halt
		 *	- bits 30:27 - Channel/EP Number
		 */
		unsigned nptxqtop_terminate:1;
		unsigned nptxqtop_token:2;
		unsigned nptxqtop_chnep:4;
		unsigned reserved:1;
	} b;
} gnptxsts_data_t;

/**
 * This union represents the bit fields in the Transmit
 * FIFO Status Register (DTXFSTS). Read the register into the
 * <i>d32</i> element then read out the bits using the <i>b</i>it
 * elements.
 */
typedef union dtxfsts_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		unsigned txfspcavail:16;
		unsigned reserved:16;
	} b;
} dtxfsts_data_t;

/**
 * This union represents the bit fields in the I2C Control Register
 * (I2CCTL). Read the register into the <i>d32</i> element then read out the
 * bits using the <i>b</i>it elements.
 */
typedef union gi2cctl_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		unsigned rwdata:8;
		unsigned regaddr:8;
		unsigned addr:7;
		unsigned i2cen:1;
		unsigned ack:1;
		unsigned i2csuspctl:1;
		unsigned i2cdevaddr:2;
		unsigned reserved:2;
		unsigned rw:1;
		unsigned bsydne:1;
	} b;
} gi2cctl_data_t;

/**
 * This union represents the bit fields in the User HW Config1
 * Register.  Read the register into the <i>d32</i> element then read
 * out the bits using the <i>b</i>it elements.
 */
typedef union hwcfg1_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		unsigned ep_dir0:2;
		unsigned ep_dir1:2;
		unsigned ep_dir2:2;
		unsigned ep_dir3:2;
		unsigned ep_dir4:2;
		unsigned ep_dir5:2;
		unsigned ep_dir6:2;
		unsigned ep_dir7:2;
		unsigned ep_dir8:2;
		unsigned ep_dir9:2;
		unsigned ep_dir10:2;
		unsigned ep_dir11:2;
		unsigned ep_dir12:2;
		unsigned ep_dir13:2;
		unsigned ep_dir14:2;
		unsigned ep_dir15:2;
	} b;
} hwcfg1_data_t;

/**
 * This union represents the bit fields in the User HW Config2
 * Register.  Read the register into the <i>d32</i> element then read
 * out the bits using the <i>b</i>it elements.
 */
typedef union hwcfg2_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		/* GHWCFG2 */
		unsigned op_mode:3;
#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6

		unsigned architecture:2;
		unsigned point2point:1;
		unsigned hs_phy_type:2;
#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3

		unsigned fs_phy_type:2;
		unsigned num_dev_ep:4;
		unsigned num_host_chan:4;
		unsigned perio_ep_supported:1;
		unsigned dynamic_fifo:1;
		unsigned rx_status_q_depth:2;
		unsigned nonperio_tx_q_depth:2;
		unsigned host_perio_tx_q_depth:2;
		unsigned dev_token_q_depth:5;
		unsigned reserved31:1;
	} b;
} hwcfg2_data_t;

/**
 * This union represents the bit fields in the User HW Config3
 * Register.  Read the register into the <i>d32</i> element then read
 * out the bits using the <i>b</i>it elements.
 */
typedef union hwcfg3_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		/* GHWCFG3 */
		unsigned xfer_size_cntr_width:4;
		unsigned packet_size_cntr_width:3;
		unsigned otg_func:1;
		unsigned i2c:1;
		unsigned vendor_ctrl_if:1;
		unsigned optional_features:1;
		unsigned synch_reset_type:1;
		unsigned ahb_phy_clock_synch:1;
		unsigned reserved15_13:3;
		unsigned dfifo_depth:16;
	} b;
} hwcfg3_data_t;

/**
 * This union represents the bit fields in the User HW Config4
 * Register.  Read the register into the <i>d32</i> element then read
 * out the bits using the <i>b</i>it elements.
 */
typedef union hwcfg4_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		unsigned num_dev_perio_in_ep:4;
		unsigned power_optimiz:1;
		unsigned min_ahb_freq:9;
		unsigned utmi_phy_data_width:2;
		unsigned num_dev_mode_ctrl_ep:4;
		unsigned iddig_filt_en:1;
		unsigned vbus_valid_filt_en:1;
		unsigned a_valid_filt_en:1;
		unsigned b_valid_filt_en:1;
		unsigned session_end_filt_en:1;
		unsigned ded_fifo_en:1;
		unsigned num_in_eps:4;
		unsigned desc_dma:1;
		unsigned desc_dma_dyn:1;
	} b;
} hwcfg4_data_t;

////////////////////////////////////////////
// Device Registers
/**
 * Device Global Registers. <i>Offsets 800h-BFFh</i>
 *
 * The following structures define the size and relative field offsets
 * for the Device Mode Registers.
 *
 * <i>These registers are visible only in Device mode and must not be
 * accessed in Host mode, as the results are unknown.</i>
 */
typedef struct dwc_otg_dev_global_regs {
	/** Device Configuration Register. <i>Offset 800h</i> */
	volatile uint32_t dcfg;
	/** Device Control Register. <i>Offset: 804h</i> */
	volatile uint32_t dctl;
	/** Device Status Register (Read Only). <i>Offset: 808h</i> */
	volatile uint32_t dsts;
	/** Reserved. <i>Offset: 80Ch</i> */
	uint32_t unused;
	/** Device IN Endpoint Common Interrupt Mask
	 * Register. <i>Offset: 810h</i> */
	volatile uint32_t diepmsk;
	/** Device OUT Endpoint Common Interrupt Mask
	 * Register. <i>Offset: 814h</i> */
	volatile uint32_t doepmsk;
	/** Device All Endpoints Interrupt Register.  <i>Offset: 818h</i> */
	volatile uint32_t daint;
	/** Device All Endpoints Interrupt Mask Register.  <i>Offset:
	 * 81Ch</i> */
	volatile uint32_t daintmsk;
	/** Device IN Token Queue Read Register-1 (Read Only).
	 * <i>Offset: 820h</i> */
	volatile uint32_t dtknqr1;
	/** Device IN Token Queue Read Register-2 (Read Only).
	 * <i>Offset: 824h</i> */
	volatile uint32_t dtknqr2;
	/** Device VBUS	 discharge Register.  <i>Offset: 828h</i> */
	volatile uint32_t dvbusdis;
	/** Device VBUS Pulse Register.	 <i>Offset: 82Ch</i> */
	volatile uint32_t dvbuspulse;
	/** Device IN Token Queue Read Register-3 (Read Only). /
	 *	Device Thresholding control register (Read/Write)
	 * <i>Offset: 830h</i> */
	volatile uint32_t dtknqr3_dthrctl;
	/** Device IN Token Queue Read Register-4 (Read Only). /
	 *	Device IN EPs empty Inr. Mask Register (Read/Write)
	 * <i>Offset: 834h</i> */
	volatile uint32_t dtknqr4_fifoemptymsk;
} dwc_otg_device_global_regs_t;

/**
 * This union represents the bit fields in the Device Configuration
 * Register.  Read the register into the <i>d32</i> member then
 * set/clear the bits using the <i>b</i>it elements.  Write the
 * <i>d32</i> member to the dcfg register.
 */
typedef union dcfg_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		/** Device Speed */
		unsigned devspd:2;
		/** Non Zero Length Status OUT Handshake */
		unsigned nzstsouthshk:1;
#define DWC_DCFG_SEND_STALL 1

		unsigned reserved3:1;
		/** Device Addresses */
		unsigned devaddr:7;
		/** Periodic Frame Interval */
		unsigned perfrint:2;
#define DWC_DCFG_FRAME_INTERVAL_80 0
#define DWC_DCFG_FRAME_INTERVAL_85 1
#define DWC_DCFG_FRAME_INTERVAL_90 2
#define DWC_DCFG_FRAME_INTERVAL_95 3

		unsigned reserved13_17:5;
		/** In Endpoint Mis-match count */
		unsigned epmscnt:5;
		/** Enable Descriptor DMA in Device mode */
		unsigned descdma:1;
	} b;
} dcfg_data_t;

/**
 * This union represents the bit fields in the Device Control
 * Register.  Read the register into the <i>d32</i> member then
 * set/clear the bits using the <i>b</i>it elements.
 */
typedef union dctl_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		/** Remote Wakeup */
		unsigned rmtwkupsig:1;
		/** Soft Disconnect */
		unsigned sftdiscon:1;
		/** Global Non-Periodic IN NAK Status */
		unsigned gnpinnaksts:1;
		/** Global OUT NAK Status */
		unsigned goutnaksts:1;
		/** Test Control */
		unsigned tstctl:3;
		/** Set Global Non-Periodic IN NAK */
		unsigned sgnpinnak:1;
		/** Clear Global Non-Periodic IN NAK */
		unsigned cgnpinnak:1;
		/** Set Global OUT NAK */
		unsigned sgoutnak:1;
		/** Clear Global OUT NAK */
		unsigned cgoutnak:1;

		/** Power-On Programming Done */
		unsigned pwronprgdone:1;
		/** Global Continue on BNA */
		unsigned gcontbna:1;
		/** Global Multi Count */
		unsigned gmc:2;
		/** Ignore Frame Number for ISOC EPs */
		unsigned ifrmnum:1;

		unsigned reserved16_31:16;
	} b;
} dctl_data_t;

/**
 * This union represents the bit fields in the Device Status
 * Register.  Read the register into the <i>d32</i> member then
 * set/clear the bits using the <i>b</i>it elements.
 */
typedef union dsts_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		/** Suspend Status */
		unsigned suspsts:1;
		/** Enumerated Speed */
		unsigned enumspd:2;
#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ		   2
#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ		   3
		/** Erratic Error */
		unsigned errticerr:1;
		unsigned reserved4_7:4;
		/** Frame or Microframe Number of the received SOF */
		unsigned soffn:14;
		unsigned reserved22_31:10;
	} b;
} dsts_data_t;


/**
 * This union represents the bit fields in the Device IN EP Interrupt
 * Register and the Device IN EP Common Mask Register.
 *
 * - Read the register into the <i>d32</i> member then set/clear the
 *	 bits using the <i>b</i>it elements.
 */
typedef union diepint_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		/** Transfer complete mask */
		unsigned xfercompl:1;
		/** Endpoint disable mask */
		unsigned epdisabled:1;
		/** AHB Error mask */
		unsigned ahberr:1;
		/** TimeOUT Handshake mask (non-ISOC EPs) */
		unsigned timeout:1;
		/** IN Token received with TxF Empty mask */
		unsigned intktxfemp:1;
		/** IN Token Received with EP mismatch mask */
		unsigned intknepmis:1;
		/** IN Endpoint HAK Effective mask */
		unsigned inepnakeff:1;
		/** IN Endpoint HAK Effective mask */
		unsigned emptyintr:1;

		unsigned txfifoundrn:1;

		/** BNA Interrupt mask */
		unsigned bna:1;
		unsigned reserved08_31:22;
	} b;
} diepint_data_t;
/**
 * This union represents the bit fields in the Device IN EP Common
 * Interrupt Mask Register.
 */
typedef union diepint_data diepmsk_data_t;

/**
 * This union represents the bit fields in the Device OUT EP Interrupt
 * Registerand Device OUT EP Common Interrupt Mask Register.
 *
 * - Read the register into the <i>d32</i> member then set/clear the
 *	 bits using the <i>b</i>it elements.
 */
typedef union doepint_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		/** Transfer complete */
		unsigned xfercompl:1;
		/** Endpoint disable  */
		unsigned epdisabled:1;
		/** AHB Error */
		unsigned ahberr:1;
		/** Setup Phase Done (contorl EPs) */
		unsigned setup:1;
		/** OUT Token Received when Endpoint Disabled */
		unsigned outtknepdis:1;

		unsigned stsphsercvd:1;
		/** Back-to-Back SETUP Packets Received */
		unsigned back2backsetup:1;

		unsigned reserved7:1;
		/** OUT packet Error */
		unsigned outpkterr:1;
		/** BNA Interrupt */
		unsigned bna:1;

		unsigned reserved10_31:22;
	} b;
} doepint_data_t;
/**
 * This union represents the bit fields in the Device OUT EP Common
 * Interrupt Mask Register.
 */
typedef union doepint_data doepmsk_data_t;


/**
 * This union represents the bit fields in the Device All EP Interrupt
 * and Mask Registers.
 * - Read the register into the <i>d32</i> member then set/clear the
 *	 bits using the <i>b</i>it elements.
 */
typedef union daint_data {
	/** raw register data */
	uint32_t d32;
	/** register bits */
	struct {
		/** IN Endpoint bits */
		unsigned in:16;