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📄 power_svpwm.mdl

📁 三相异步电机的SVPWM转差频率闭环调速系统的matlab实现
💻 MDL
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	      Name		      "Discrete\nVariable Frequency\nMean valu"
"e1"
	      Ports		      [2, 1]
	      Position		      [400, 123, 460, 192]
	      NamePlacement	      "alternate"
	      DialogController	      "POWERSYS.PowerSysDialog"
	      SourceBlock	      "powerlib_extras/Discrete\nMeasurements/"
"Discrete\nVariable Frequency\nMean value"
	      SourceType	      "Discrete Variable-Frequency Mean Value"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData "off"
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      Finit		      "Finit"
	      Fmin		      "20"
	      Vinit		      "Real_Init"
	      Ts		      "Ts"
	      Port {
		PortNumber		1
		Name			"Real"
		RTWStorageClass		"Auto"
		DataLoggingNameMode	"SignalName"
	      }
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Discrete\nVariable Frequency\nMean valu"
"e2"
	      Ports		      [2, 1]
	      Position		      [400, 238, 460, 307]
	      DialogController	      "POWERSYS.PowerSysDialog"
	      SourceBlock	      "powerlib_extras/Discrete\nMeasurements/"
"Discrete\nVariable Frequency\nMean value"
	      SourceType	      "Discrete Variable-Frequency Mean Value"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData "off"
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      Finit		      "Finit"
	      Fmin		      "20"
	      Vinit		      "Imag_Init"
	      Ts		      "Ts"
	      Port {
		PortNumber		1
		Name			"Imag"
		RTWStorageClass		"Auto"
		DataLoggingNameMode	"SignalName"
	      }
	    }
	    Block {
	      BlockType		      Fcn
	      Name		      "Fcn3"
	      Position		      [570, 183, 690, 207]
	      ShowName		      off
	      Expr		      "sqrt(u[1]*u[1]+u[2]*u[2])"
	    }
	    Block {
	      BlockType		      Fcn
	      Name		      "Fcn4"
	      Position		      [570, 233, 710, 257]
	      ShowName		      off
	      Expr		      "atan2(u[2]+1e-6,u[1])*180/pi"
	    }
	    Block {
	      BlockType		      Gain
	      Name		      "Gain1"
	      Position		      [165, 219, 195, 251]
	      ShowName		      off
	      Gain		      "2"
	    }
	    Block {
	      BlockType		      Mux
	      Name		      "Mux1"
	      Ports		      [2, 1]
	      Position		      [515, 175, 520, 250]
	      ShowName		      off
	      Inputs		      "2"
	    }
	    Block {
	      BlockType		      Product
	      Name		      "Product"
	      Ports		      [2, 1]
	      Position		      [235, 175, 270, 255]
	      CollapseMode	      "All dimensions"
	      RndMeth		      "Floor"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Mag"
	      Position		      [735, 188, 765, 202]
	      IconDisplay	      "Port number"
	      BusOutputAsStruct	      off
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Phase"
	      Position		      [740, 238, 770, 252]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      BusOutputAsStruct	      off
	    }
	    Line {
	      SrcBlock		      "Mux1"
	      SrcPort		      1
	      Points		      [25, 0]
	      Branch {
		Points			[0, -20]
		DstBlock		"Fcn3"
		DstPort			1
	      }
	      Branch {
		Points			[0, 30]
		DstBlock		"Fcn4"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Fcn3"
	      SrcPort		      1
	      DstBlock		      "Mag"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Fcn4"
	      SrcPort		      1
	      DstBlock		      "Phase"
	      DstPort		      1
	    }
	    Line {
	      Name		      "Imag"
	      Labels		      [0, 0]
	      SrcBlock		      "Discrete\nVariable Frequency\nMean valu"
"e2"
	      SrcPort		      1
	      Points		      [35, 0]
	      DstBlock		      "Mux1"
	      DstPort		      2
	    }
	    Line {
	      Name		      "Real"
	      Labels		      [0, 0]
	      SrcBlock		      "Discrete\nVariable Frequency\nMean valu"
"e1"
	      SrcPort		      1
	      Points		      [35, 0]
	      DstBlock		      "Mux1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Demux"
	      SrcPort		      1
	      Points		      [25, 0; 0, -30]
	      DstBlock		      "Discrete\nVariable Frequency\nMean valu"
"e1"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Gain1"
	      SrcPort		      1
	      DstBlock		      "Product"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Product"
	      SrcPort		      1
	      DstBlock		      "Demux"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Demux"
	      SrcPort		      2
	      Points		      [30, 0; 0, 65]
	      DstBlock		      "Discrete\nVariable Frequency\nMean valu"
"e2"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Freq"
	      SrcPort		      1
	      Points		      [265, 0]
	      Branch {
		Points			[0, 115]
		DstBlock		"Discrete\nVariable Frequency\nMean va"
"lue2"
		DstPort			1
	      }
	      Branch {
		DstBlock		"Discrete\nVariable Frequency\nMean va"
"lue1"
		DstPort			1
	      }
	    }
	    Line {
	      SrcBlock		      "Sin_Cos"
	      SrcPort		      1
	      DstBlock		      "Gain1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      DstBlock		      "Product"
	      DstPort		      1
	    }
	    Annotation {
	      Name		      "Discrete PLL-Driven Fundamental Value"
	      Position		      [161, 28]
	      FontSize		      12
	      FontWeight	      "bold"
	    }
	    Annotation {
	      Name		      "Pierre Giroux, Gilbert Sybille\nPower S"
"ystem Simulation Laboratory\nIREQ, Hydro-Quebec"
	      Position		      [147, 61]
	    }
	  }
	}
	Block {
	  BlockType		  Reference
	  Name			  "Discrete \n2nd-Order\nFilter1"
	  Ports			  [1, 1]
	  Position		  [200, 69, 250, 111]
	  DialogController	  "POWERSYS.PowerSysDialog"
	  SourceBlock		  "powerlib_extras/Discrete \nControl Blocks/D"
"iscrete \n2nd-Order\nFilter"
	  SourceType		  "Discrete 2nd-Order Filter"
	  ShowPortLabels	  "FromPortIcon"
	  SystemSampleTime	  "-1"
	  FunctionWithSeparateData "off"
	  RTWMemSecFuncInitTerm	  "Inherit from model"
	  RTWMemSecFuncExecute	  "Inherit from model"
	  RTWMemSecDataConstants  "Inherit from model"
	  RTWMemSecDataInternal	  "Inherit from model"
	  RTWMemSecDataParameters "Inherit from model"
	  FilterType		  "Lowpass"
	  Fo			  "2000"
	  Zeta			  "0.707"
	  Ts			  "Ts"
	  Initialize		  "on"
	  Vac_Init		  "[1 30 60]"
	  Vdc_Init		  "0"
	  PlotResponse		  "off"
	  param1		  "[1 500 1]"
	}
	Block {
	  BlockType		  From
	  Name			  "From"
	  Position		  [45, 77, 115, 103]
	  ShowName		  off
	  CloseFcn		  "tagdialog Close"
	  GotoTag		  "Vabc_Stator"
	}
	Block {
	  BlockType		  From
	  Name			  "From1"
	  Position		  [55, 192, 125, 218]
	  ShowName		  off
	  CloseFcn		  "tagdialog Close"
	  GotoTag		  "Iabc_Stator"
	}
	Block {
	  BlockType		  From
	  Name			  "From3"
	  Position		  [70, 256, 110, 284]
	  ShowName		  off
	  CloseFcn		  "tagdialog Close"
	  GotoTag		  "m"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "PLL"
	  Ports			  [1, 3]
	  Position		  [340, 38, 420, 142]
	  DropShadow		  on
	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  MaskHideContents	  off
	  MaskType		  "Discrete 1-phase PLL"
	  MaskDescription	  "This Phase Locked Loop (PLL) system can be "
"used  to synchronize on a variable frequency sinusoidal signal.\n\nInput 1: N"
"ormalized input signal V(pu)\n\nOutput 1:  Measured frequency (Hz) = w/(2pi)"
"\nOutput 2:  Ramp w.t  varying between  0 and 2*pi, synchronized on the zero-"
"crossing (rising) of  the input signal\nOutput 3: Vector [sin(wt) cos(wt)]\n"
	  MaskPromptString	  "Initial input:[ Phase(degrees)   Frequency("
"Hz) ]|Regulator gains [ Kp  Ki ]|Sample time:"
	  MaskStyleString	  "edit,edit,edit"
	  MaskTunableValueString  "on,on,on"
	  MaskCallbackString	  "||"
	  MaskEnableString	  "on,on,on"
	  MaskVisibilityString	  "on,on,on"
	  MaskToolTipString	  "on,on,on"
	  MaskVarAliasString	  ",,"
	  MaskVariables		  "Par_Init=@1;ParK=@2;Ts=@3;"
	  MaskInitialization	  "Kp=ParK(1);\nKi=ParK(2);\nPhase_Init=Par_In"
"it(1);\nFinit=Par_Init(2);"
	  MaskIconFrame		  on
	  MaskIconOpaque	  on
	  MaskIconRotate	  "none"
	  MaskIconUnits		  "autoscale"
	  MaskValueString	  "[27.52 60]|[120 2800]|Ts*20"
	  MaskTabNameString	  ",,"
	  System {
	    Name		    "PLL"
	    Location		    [555, 204, 1441, 744]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "V(pu)"
	      Position		      [50, 233, 80, 247]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Constant
	      Name		      "Constant4"
	      Position		      [455, 275, 485, 295]
	      NamePlacement	      "alternate"
	      ShowName		      off
	      Value		      "2*pi"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Discrete\nPI Controller"
	      Ports		      [1, 1]
	      Position		      [310, 222, 355, 268]
	      DialogController	      "POWERSYS.PowerSysDialog"
	      SourceBlock	      "powerlib_extras/Discrete \nControl Bloc"
"ks/Discrete\nPI Controller"
	      SourceType	      "Discrete PI Controller"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData "off"
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      Kp		      "Kp"
	      Ki		      "Ki"
	      Par_Limits	      "[4  0.25]*2*pi*Finit"
	      Init		      "2*pi*Finit"
	      Ts		      "Ts"
	      Port {
		PortNumber		1
		Name			"W"
		RTWStorageClass		"Auto"
		DataLoggingNameMode	"SignalName"
	      }
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Discrete\nRate Limiter"
	      Ports		      [1, 1]
	      Position		      [525, 121, 575, 169]
	      DialogController	      "POWERSYS.PowerSysDialog"
	      SourceBlock	      "powerlib_extras/Discrete \nControl Bloc"
"ks/Discrete\nRate Limiter"
	      SourceType	      "Discrete Rate Limiter"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData "off"
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      R			      "30"
	      F			      "-30"
	      Vinit		      "Finit"
	      Ts		      "Ts"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Discrete\nVariable Frequency\nMean valu"
"e"
	      Ports		      [2, 1]
	      Position		      [205, 208, 265, 277]
	      DialogController	      "POWERSYS.PowerSysDialog"
	      SourceBlock	      "powerlib_extras/Discrete\nMeasurements/"
"Discrete\nVariable Frequency\nMean value"
	      SourceType	      "Discrete Variable-Frequency Mean Value"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData "off"
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      Finit		      "Finit"
	      Fmin		      "10"
	      Vinit		      "0"
	      Ts		      "Ts"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Discrete \n2nd-Order\nFilter"
	      Ports		      [1, 1]
	      Position		      [610, 114, 665, 176]
	      DialogController	      "POWERSYS.PowerSysDialog"
	      SourceBlock	      "powerlib_extras/Discrete \nControl Bloc"
"ks/Discrete \n2nd-Order\nFilter"
	      SourceType	      "Discrete 2nd-Order Filter"
	      ShowPortLabels	      "FromPortIcon"
	      SystemSampleTime	      "-1"
	      FunctionWithSeparateData "off"
	      RTWMemSecFuncInitTerm   "Inherit from model"
	      RTWMemSecFuncExecute    "Inherit from model"
	      RTWMemSecDataConstants  "Inherit from model"
	      RTWMemSecDataInternal   "Inherit from model"
	      RTWMemSecDataParameters "Inherit from model"
	      FilterType	      "Lowpass"
	      Fo		      "25"
	      Zeta		      "0.707"
	      Ts		      "Ts"
	      Initialize	      "on"
	      Vac_Init		      "[0 0  Finit]"
	      Vdc_Init		      "Finit"
	      PlotResponse	      "off"
	      param1		      "[1 500 0.1]"
	    }
	    Block {
	      BlockType		      DiscreteIntegrator
	      Name		      "Discrete-Time\nIntegrator"
	      Ports		      [1, 1]
	      Position		      [425, 227, 465, 263]
	      ShowName		      off
	      IntegratorMethod	      "Integration: Forward Euler"
	      ExternalReset	      "none"
	      InitialConditionSource  "internal"
	      InitialCondition	      "Phase_Init*pi/180"
	      SampleTime	      "Ts"
	      UpperSaturationLimit    "0"
	      LowerSaturationLimit    "0"
	      IgnoreLimit	      off
	      ICPrevOutput	      "DiscIntNeverNeededParam"

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