liveosci.asm

10MS/s USB-2.0 ("high speed") oscilloscope with two 8 bit sampling inputs

_FLOWEQ1CTL	=	0xe6c9
_FLOWHOLDOFF	=	0xe6ca
_FLOWSTB	=	0xe6cb
_FLOWSTBEDGE	=	0xe6cc
_FLOWSTBHPERIOD	=	0xe6cd
_GPIFHOLDAMOUNT	=	0xe60c
_UDMACRCH	=	0xe67d
_UDMACRCL	=	0xe67e
_UDMACRCQUAL	=	0xe67f
_DBUG	=	0xe6f8
_TESTCFG	=	0xe6f9
_USBTEST	=	0xe6fa
_CT1	=	0xe6fb
_CT2	=	0xe6fc
_CT3	=	0xe6fd
_CT4	=	0xe6fe
_EP0BUF	=	0xe740
_EP1OUTBUF	=	0xe780
_EP1INBUF	=	0xe7c0
_EP2FIFOBUF	=	0xf000
_EP4FIFOBUF	=	0xf400
_EP6FIFOBUF	=	0xf800
_EP8FIFOBUF	=	0xfc00
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
	.area XISEG   (XDATA)
;--------------------------------------------------------
; interrupt vector 
;--------------------------------------------------------
	.area CSEG    (CODE)
__interrupt_vect:
	ljmp	__sdcc_gsinit_startup
	reti
	.ds	7
	reti
	.ds	7
	reti
	.ds	7
	reti
	.ds	7
	reti
	.ds	7
	reti
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
	.area GSINIT  (CODE)
	.area GSFINAL (CODE)
	.area GSINIT  (CODE)
__sdcc_gsinit_startup:
	mov	sp,#__start__stack - 1
	lcall	__sdcc_external_startup
	mov	a,dpl
	jz	__sdcc_init_data
	ljmp	__sdcc_program_startup
__sdcc_init_data:
;	_mcs51_genXINIT() start
	mov	r1,#l_XINIT
	mov	a,r1
	orl	a,#(l_XINIT >> 8)
	jz	00003$
	mov	r2,#((l_XINIT+255) >> 8)
	mov	dptr,#s_XINIT
	mov	r0,#s_XISEG
	mov	p2,#(s_XISEG >> 8)
00001$:	clr	a
	movc	a,@a+dptr
	movx	@r0,a
	inc	dptr
	inc	r0
	cjne	r0,#0,00002$
	inc	p2
00002$:	djnz	r1,00001$
	djnz	r2,00001$
	mov	p2,#0xFF
00003$:
;	_mcs51_genXINIT() end
;	_mcs51_genRAMCLEAR() start
	mov	r0,#l_XSEG
	mov	a,r0
	orl	a,#(l_XSEG >> 8)
	jz	00005$
	mov	r1,#((l_XSEG + 255) >> 8)
	mov	dptr,#s_XSEG
	clr     a
00004$:	movx	@dptr,a
	inc	dptr
	djnz	r0,00004$
	djnz	r1,00004$
00005$:	mov	@r0,a
	djnz	r0,00005$
;	_mcs51_genRAMCLEAR() end
;liveosci.c:34: static uint8 iomodule_config=0x00U;
;     genAssign
	mov	_iomodule_config,#0x00
	.area GSFINAL (CODE)
	ljmp	__sdcc_program_startup
;--------------------------------------------------------
; Home
;--------------------------------------------------------
	.area HOME    (CODE)
	.area CSEG    (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
	.area CSEG    (CODE)
__sdcc_program_startup:
	lcall	_main
;	return from main will lock up
	sjmp .
;------------------------------------------------------------
;Allocation info for local variables in function 'Initialize'
;------------------------------------------------------------
;------------------------------------------------------------
;liveosci.c:85: static void Initialize(void)
;	-----------------------------------------
;	 function Initialize
;	-----------------------------------------
_Initialize:
	ar2 = 0x02
	ar3 = 0x03
	ar4 = 0x04
	ar5 = 0x05
	ar6 = 0x06
	ar7 = 0x07
	ar0 = 0x00
	ar1 = 0x01
;liveosci.c:87: SYNCDELAY;
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:97: CPUCS = 0x12;  // 0x12
;     genAssign
	mov	dptr,#_CPUCS
	mov	a,#0x12
	movx	@dptr,a
;liveosci.c:98: SYNCDELAY;
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:103: IOA=0x00U;
;     genAssign
	mov	_IOA,#0x00
;liveosci.c:104: OEA|=(1U<<1)|(1U<<3)|(1U<<7);
;     genOr
	orl	_OEA,#0x8A
;liveosci.c:105: IOA=0x00U;
;     genAssign
	mov	_IOA,#0x00
;liveosci.c:117: IFCONFIG = 0x43; // 0100 0011 = 0x43   externally clocked sync mode
;     genAssign
	mov	dptr,#_IFCONFIG
	mov	a,#0x43
	movx	@dptr,a
;liveosci.c:120: SYNCDELAY;
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:123: REVCTL = 0x03;  // See TRM...
;     genAssign
	mov	dptr,#_REVCTL
	mov	a,#0x03
	movx	@dptr,a
;liveosci.c:124: SYNCDELAY;
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:135: EP6CFG = 0xe0;  // bulk: 0xe2 double-buffered; 0xe3 triple-; 0xe0 quad
;     genAssign
	mov	dptr,#_EP6CFG
	mov	a,#0xE0
	movx	@dptr,a
;liveosci.c:136: SYNCDELAY;
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:148: EP1OUTCFG = 0xa2;
;     genAssign
	mov	dptr,#_EP1OUTCFG
	mov	a,#0xA2
	movx	@dptr,a
;liveosci.c:153: EP1INCFG = 0xe2;
;     genAssign
	mov	dptr,#_EP1INCFG
	mov	a,#0xE2
	movx	@dptr,a
;liveosci.c:157: FIFORESET = 0x80;  SYNCDELAY;  // NAK all requests from host. 
;     genAssign
	mov	dptr,#_FIFORESET
	mov	a,#0x80
	movx	@dptr,a
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:158: FIFORESET = 0x02;  SYNCDELAY;  // Reset individual EP (2,4,6,8)
;     genAssign
	mov	dptr,#_FIFORESET
	mov	a,#0x02
	movx	@dptr,a
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:159: FIFORESET = 0x04;  SYNCDELAY;
;     genAssign
	mov	dptr,#_FIFORESET
	mov	a,#0x04
	movx	@dptr,a
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:160: FIFORESET = 0x06;  SYNCDELAY;
;     genAssign
	mov	dptr,#_FIFORESET
	mov	a,#0x06
	movx	@dptr,a
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:161: FIFORESET = 0x08;  SYNCDELAY;
;     genAssign
	mov	dptr,#_FIFORESET
	mov	a,#0x08
	movx	@dptr,a
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:162: FIFORESET = 0x00;  SYNCDELAY;  // Resume normal operation. 
;     genAssign
	mov	dptr,#_FIFORESET
;       Peephole 181    changed mov to clr
	clr     a
	movx	@dptr,a
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:174: EP6FIFOCFG = 0x0d /*&0xfe*/;
;     genAssign
	mov	dptr,#_EP6FIFOCFG
	mov	a,#0x0D
	movx	@dptr,a
;liveosci.c:175: SYNCDELAY;
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:187: PORTACFG = 0x00;
;     genAssign
	mov	dptr,#_PORTACFG
;       Peephole 181    changed mov to clr
	clr     a
	movx	@dptr,a
;liveosci.c:188: SYNCDELAY; // maybe not needed
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:191: FIFOPINPOLAR=0x00;
;     genAssign
	mov	dptr,#_FIFOPINPOLAR
;       Peephole 181    changed mov to clr
	clr     a
	movx	@dptr,a
;liveosci.c:192: SYNCDELAY;
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:197: EP6AUTOINLENH = 0x02; // MSB
;     genAssign
	mov	dptr,#_EP6AUTOINLENH
	mov	a,#0x02
	movx	@dptr,a
;liveosci.c:198: SYNCDELAY;
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
;liveosci.c:199: EP6AUTOINLENL = 0x00; // LSB
;     genAssign
	mov	dptr,#_EP6AUTOINLENL
;       Peephole 181    changed mov to clr
	clr     a
	movx	@dptr,a
;liveosci.c:200: SYNCDELAY;
;     genInline
	 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; 
00101$:
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'CkGen_SerialIOByte'
;------------------------------------------------------------
;to_send                   Allocated to registers r2 
;i                         Allocated to registers 
;j                         Allocated to registers 
;res                       Allocated to registers r3 
;------------------------------------------------------------
;liveosci.c:215: static uint8 CkGen_SerialIOByte(uint8 to_send)
;	-----------------------------------------
;	 function CkGen_SerialIOByte
;	-----------------------------------------
_CkGen_SerialIOByte:
;     genReceive
	mov	r2,dpl
;liveosci.c:218: uint8 res=0U;
;     genAssign
	mov	r3,#0x00
;liveosci.c:220: for(i=0; i<8; i++)
;     genAssign
	mov	r4,#0x00
00124$:
;     genCmpLt
;     genCmp
	cjne	r4,#0x08,00138$
00138$:
;     genIfxJump
;       Peephole 108    removed ljmp by inverse jump logic
	jnc     00127$
00139$:
;liveosci.c:222: res<<=1;
;     genLeftShift
;     genLeftShiftLiteral
;     genlshOne
	mov	a,r3
	add	a,acc
	mov	r3,a
;liveosci.c:225: if(to_send & (0x80U>>i))  SET_TXD_HIGH();
;     genRightShift
	mov	b,r4
	inc	b
	mov	r5,#0x80
	mov	r6,#0x00
	sjmp	00141$
00140$:
	clr	c
	mov	a,r6
	rrc	a
	mov	r6,a
	mov	a,r5
	rrc	a
	mov	r5,a
00141$:
	djnz	b,00140$
;     genCast
	mov	ar7,r2
	mov	r0,#0x00
;     genAnd
	mov	a,r7
	anl	ar5,a
	mov	a,r0
	anl	ar6,a
;     genIfx
	mov	a,r5
	orl	a,r6
;     genIfxJump
;       Peephole 110    removed ljmp by inverse jump logic
	jz      00104$
00142$:
;     genOr
	orl	_IOA,#0x80
;liveosci.c:226: else                      SET_TXD_LOW();
;       Peephole 112.b  changed ljmp to sjmp
	sjmp    00110$
00104$:
;     genAssign
	mov	r5,_IOA
;     genAnd
	mov	a,#0x7F
	anl	a,r5
	mov	_IOA,a
;liveosci.c:227: SET_SCK_HIGH();
00110$:
;     genOr
	orl	_IOA,#0x08
;liveosci.c:231: for(j=0; j<8; j++) { NOP; }
;     genAssign
	mov	r5,#0x08
00120$:
;     genInline
	 nop; 
;     genDjnz
;       Peephole 112.b  changed ljmp to sjmp
;       Peephole 205    optimized misc jump sequence
	djnz    r5,00120$
00143$:
00144$:
;liveosci.c:234: SET_SCK_LOW();
;     genAssign
	mov	r5,_IOA
;     genAnd
	mov	a,#0xF7
	anl	a,r5
	mov	_IOA,a
;liveosci.c:237: if(RXD_LEVEL())  res|=1;
;     genAnd
	mov	a,_IOA
;     genIfxJump
;       Peephole 111    removed ljmp by inverse jump logic
	jnb     acc.0,00135$
00145$:
;     genOr
	orl	ar3,#0x01
;liveosci.c:240: for(j=0; j<8; j++) { NOP; }
00135$:
;     genAssign
	mov	r5,#0x08
00123$:
;     genInline
	 nop; 
;     genDjnz
;       Peephole 112.b  changed ljmp to sjmp
;       Peephole 205    optimized misc jump sequence
	djnz    r5,00123$
00146$:
00147$:
;liveosci.c:220: for(i=0; i<8; i++)
;     genPlus
;     genPlusIncr
	inc	r4
;       Peephole 112.b  changed ljmp to sjmp
	sjmp    00124$
00127$:
;liveosci.c:243: return(res);
;     genRet
	mov	dpl,r3
00128$:
	ret
;------------------------------------------------------------
;Allocation info for local variables in function 'WriteIOModuleConfig'
;------------------------------------------------------------
;keep_rck_high             Allocated to registers r2 
;i                         Allocated to registers 
;config                    Allocated to registers r3 
;tmp                       Allocated to registers r2 
;------------------------------------------------------------
;liveosci.c:247: static void WriteIOModuleConfig(uint8 keep_rck_high)
;	-----------------------------------------
;	 function WriteIOModuleConfig
;	-----------------------------------------
_WriteIOModuleConfig:
;     genReceive
	mov	r2,dpl
;liveosci.c:252: uint8 i,config=iomodule_config;
;     genAssign
	mov	r3,_iomodule_config
;liveosci.c:255: SET_CKGEN_INT1_SREG_RCK_LOW();
;     genAssign
	mov	r4,_IOA
;     genAnd
	mov	a,#0xFD
	anl	a,r4
	mov	_IOA,a
;liveosci.c:256: SET_SCK_LOW();
;     genAssign
	mov	r4,_IOA
;     genAnd
	mov	a,#0xF7
	anl	a,r4
	mov	_IOA,a
;liveosci.c:258: for(i=0; i<8; i++)
;     genAssign
	mov	r4,#0x00