📄 fx2regs.h
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//sbit CT1 = 0x89+6;
//sbit GATE1 = 0x89+7;
sfr at 0x8A TL0 ;
sfr at 0x8B TL1 ;
sfr at 0x8C TH0 ;
sfr at 0x8D TH1 ;
sfr at 0x8E CKCO;
/* CKCON */
//sbit MD0 = 0x89+0;
//sbit MD1 = 0x89+1;
//sbit MD2 = 0x89+2;
//sbit T0M = 0x89+3;
//sbit T1M = 0x89+4;
//sbit T2M = 0x89+5;
sfr at 0x8F SPC_; // Was WRS in Reg320
/* CKCON */
//sbit WRS = 0x8F+0;
sfr at 0x90 IOB ;
sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320
/* EXIF */
//sbit USBINT = 0x91+4;
//sbit I2CINT = 0x91+5;
//sbit IE4 = 0x91+6;
//sbit IE5 = 0x91+7;
sfr at 0x92 MPA;
sfr at 0x98 SCO;
/* SCON0 */
/* sbit RI = 0x98+0;
sbit TI = 0x98+1;
sbit RB8 = 0x98+2;
sbit TB8 = 0x98+3;
sbit REN = 0x98+4;
sbit SM2 = 0x98+5;
sbit SM1 = 0x98+6;
sbit SM0 = 0x98+7;*/
sfr at 0x99 SBU;
sfr at 0x9A APTR1H ;
sfr at 0x9B APTR1L ;
sfr at 0x9C AUTODAT1;
sfr at 0x9D AUTOPTRH2;
sfr at 0x9E AUTOPTRL2;
sfr at 0x9F AUTODAT2;
sfr at 0xA0 IOC ;
sfr at 0xA1 INT2CLR;
sfr at 0xA2 INT4CLR;
sfr at 0xA8 IE ;
/* IE */
// sbit EX0 = 0xA8+0;
// sbit ET0 = 0xA8+1;
// sbit EX1 = 0xA8+2;
// sbit ET1 = 0xA8+3;
// sbit ES0 = 0xA8+4;
// sbit ET2 = 0xA8+5;
// sbit ES1 = 0xA8+6;
// sbit EA = 0xA8+7;
sfr at 0xAA EP2468STAT;
/* EP2468STAT */
//sbit EP2E = 0xAA+0;
//sbit EP2F = 0xAA+1;
//sbit EP4E = 0xAA+2;
//sbit EP4F = 0xAA+3;
//sbit EP6E = 0xAA+4;
//sbit EP6F = 0xAA+5;
//sbit EP8E = 0xAA+6;
//sbit EP8F = 0xAA+7;
sfr at 0xAB EP24FIFOFLGS;
sfr at 0xAC EP68FIFOFLGS;
sfr at 0xAF AUTOPTRSETUP;
/* AUTOPTRSETUP */
// sbit EXTACC = 0xAF+0;
// sbit APTR1FZ = 0xAF+1;
// sbit APTR2FZ = 0xAF+2;
sfr at 0xB0 IOD ;
sfr at 0xB1 IOE ;
sfr at 0xB2 OEA ;
sfr at 0xB3 OEB ;
sfr at 0xB4 OEC ;
sfr at 0xB5 OED ;
sfr at 0xB6 OEE ;
sfr at 0xB8 IP ;
/* IP */
// sbit PX0 = 0xB8+0;
// sbit PT0 = 0xB8+1;
// sbit PX1 = 0xB8+2;
// sbit PT1 = 0xB8+3;
// sbit PS0 = 0xB8+4;
// sbit PT2 = 0xB8+5;
// sbit PS1 = 0xB8+6;
sfr at 0xBA EP01STAT;
sfr at 0xBB GPIFTRIG;
sfr at 0xBD GPIFSGLDATH;
sfr at 0xBE GPIFSGLDATLX;
sfr at 0xBF GPIFSGLDATLNOX;
sfr at 0xC0 SCON1;
/* SCON1 */
/* sbit RI1 = 0xC0+0;
sbit TI1 = 0xC0+1;
sbit RB81 = 0xC0+2;
sbit TB81 = 0xC0+3;
sbit REN1 = 0xC0+4;
sbit SM21 = 0xC0+5;
sbit SM11 = 0xC0+6;
sbit SM01 = 0xC0+7;*/
sfr at 0xC1 SBUF1;
sfr at 0xC8 T2CON;
/* T2CON */
/* sbit CP_RL2 = 0xC8+0;
sbit C_T2 = 0xC8+1;
sbit TR2 = 0xC8+2;
sbit EXEN2 = 0xC8+3;
sbit TCLK = 0xC8+4;
sbit RCLK = 0xC8+5;
sbit EXF2 = 0xC8+6;
sbit TF2 = 0xC8+7;*/
sfr at 0xCA RCAP2L;
sfr at 0xCB RCAP2H;
sfr at 0xCC TL2;
sfr at 0xCD TH2;
sfr at 0xD0 PSW;
/* PSW */
/* sbit P = 0xD0+0;
sbit FL = 0xD0+1;
sbit OV = 0xD0+2;
sbit RS0 = 0xD0+3;
sbit RS1 = 0xD0+4;
sbit F0 = 0xD0+5;
sbit AC = 0xD0+6;
sbit CY = 0xD0+7;*/
sfr at 0xD8 EICON; // Was WDCON in DS80C320; Bit Values differ from Reg320
/* EICON */
/* sbit INT6 = 0xD8+3;
sbit RESI = 0xD8+4;
sbit ERESI = 0xD8+5;
sbit SMOD1 = 0xD8+7;*/
sfr at 0xE0 ACC;
sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320
/* EIE */
/* sbit EUSB = 0xE8+0;
sbit EI2C = 0xE8+1;
sbit EIEX4 = 0xE8+2;
sbit EIEX5 = 0xE8+3;
sbit EIEX6 = 0xE8+4;*/
sfr at 0xF0 B ;
sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
/* EIP */
// sbit PUSB = 0xF8+0;
// sbit PI2C = 0xF8+1;
// sbit EIPX4 = 0xF8+2;
// sbit EIPX5 = 0xF8+3;
// sbit EIPX6 = 0xF8+4;
/*-----------------------------------------------------------------------------
Bit Masks
-----------------------------------------------------------------------------*/
#define bmBIT0 1
#define bmBIT1 2
#define bmBIT2 4
#define bmBIT3 8
#define bmBIT4 16
#define bmBIT5 32
#define bmBIT6 64
#define bmBIT7 128
/* CPU Control & Status Register (CPUCS) */
#define bmPRTCSTB bmBIT5
#define bmCLKSPD (bmBIT4 | bmBIT3)
#define bmCLKSPD1 bmBIT4
#define bmCLKSPD0 bmBIT3
#define bmCLKINV bmBIT2
#define bmCLKOE bmBIT1
#define bm8051RES bmBIT0
/* Port Alternate Configuration Registers */
/* Port A (PORTACFG) */
#define bmFLAGD bmBIT7
#define bmINT1 bmBIT1
#define bmINT0 bmBIT0
/* Port C (PORTCCFG) */
#define bmGPIFA7 bmBIT7
#define bmGPIFA6 bmBIT6
#define bmGPIFA5 bmBIT5
#define bmGPIFA4 bmBIT4
#define bmGPIFA3 bmBIT3
#define bmGPIFA2 bmBIT2
#define bmGPIFA1 bmBIT1
#define bmGPIFA0 bmBIT0
/* Port E (PORTECFG) */
#define bmGPIFA8 bmBIT7
#define bmT2EX bmBIT6
#define bmINT6 bmBIT5
#define bmRXD1OUT bmBIT4
#define bmRXD0OUT bmBIT3
#define bmT2OUT bmBIT2
#define bmT1OUT bmBIT1
#define bmT0OUT bmBIT0
/* I2C Control & Status Register (I2CS) */
#define bmSTART bmBIT7
#define bmSTOP bmBIT6
#define bmLASTRD bmBIT5
#define bmID (bmBIT4 | bmBIT3)
#define bmBERR bmBIT2
#define bmACK bmBIT1
#define bmDONE bmBIT0
/* I2C Control Register (I2CTL) */
#define bmSTOPIE bmBIT1
#define bm400KHZ bmBIT0
/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
#define bmIV4 bmBIT6
#define bmIV3 bmBIT5
#define bmIV2 bmBIT4
#define bmIV1 bmBIT3
#define bmIV0 bmBIT2
/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
#define bmEP0ACK bmBIT6
#define bmHSGRANT bmBIT5
#define bmURES bmBIT4
#define bmSUSP bmBIT3
#define bmSUTOK bmBIT2
#define bmSOF bmBIT1
#define bmSUDAV bmBIT0
/* Breakpoint register (BREAKPT) */
#define bmBREAK bmBIT3
#define bmBPPULSE bmBIT2
#define bmBPEN bmBIT1
/* Interrupt 2 & 4 Setup (INTSETUP) */
#define bmAV2EN bmBIT3
#define INT4IN bmBIT1
#define bmAV4EN bmBIT0
/* USB Control & Status Register (USBCS) */
#define bmHSM bmBIT7
#define bmDISCON bmBIT3
#define bmNOSYNSOF bmBIT2
#define bmRENUM bmBIT1
#define bmSIGRESUME bmBIT0
/* Wakeup Control and Status Register (WAKEUPCS) */
#define bmWU2 bmBIT7
#define bmWU bmBIT6
#define bmWU2POL bmBIT5
#define bmWUPOL bmBIT4
#define bmDPEN bmBIT2
#define bmWU2EN bmBIT1
#define bmWUEN bmBIT0
/* End Point 0 Control & Status Register (EP0CS) */
#define bmHSNAK bmBIT7
/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
#define bmEPBUSY bmBIT1
#define bmEPSTALL bmBIT0
/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
#define bmEPFULL bmBIT3
#define bmEPEMPTY bmBIT2
/* Endpoint Status (EP2468STAT) SFR bits */
#define bmEP8FULL bmBIT7
#define bmEP8EMPTY bmBIT6
#define bmEP6FULL bmBIT5
#define bmEP6EMPTY bmBIT4
#define bmEP4FULL bmBIT3
#define bmEP4EMPTY bmBIT2
#define bmEP2FULL bmBIT1
#define bmEP2EMPTY bmBIT0
/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
#define bmSDPAUTO bmBIT0
/* Endpoint Data Toggle Control (TOGCTL) */
#define bmQUERYTOGGLE bmBIT7
#define bmSETTOGGLE bmBIT6
#define bmRESETTOGGLE bmBIT5
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
#define bmEP8IBN bmBIT5
#define bmEP6IBN bmBIT4
#define bmEP4IBN bmBIT3
#define bmEP2IBN bmBIT2
#define bmEP1IBN bmBIT1
#define bmEP0IBN bmBIT0
/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
#define bmEP8PING bmBIT7
#define bmEP6PING bmBIT6
#define bmEP4PING bmBIT5
#define bmEP2PING bmBIT4
#define bmEP1PING bmBIT3
#define bmEP0PING bmBIT2
#define bmIBN bmBIT0
/* Interface Configuration bits (IFCONFIG) */
#define bmIFCLKSRC bmBIT7
#define bm3048MHZ bmBIT6
#define bmIFCLKOE bmBIT5
#define bmIFCLKPOL bmBIT4
#define bmASYNC bmBIT3
#define bmGSTATE bmBIT2
#define bmIFCFG1 bmBIT1
#define bmIFCFG0 bmBIT0
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
#define bmIFGPIF bmIFCFG1
/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
#define bmINFM bmBIT6
#define bmOEP bmBIT5
#define bmAUTOOUT bmBIT4
#define bmAUTOIN bmBIT3
#define bmZEROLENIN bmBIT2
#define bmWORDWIDE bmBIT0
/* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specidic
features */
#define bmNOAUTOARM bmBIT1
#define bmSKIPCOMMIT bmBIT0
/* Fifo Reset bits (FIFORESET) */
#define bmNAKALL bmBIT7
#endif /* FX2REGS_H */
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