mycount.vhd

独立数码管计数

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mycount is
  port (clk:in std_logic;
          s1,s2:out bit;
          y1,y2:out std_logic_vector(6 downto 0));
end mycount;
architecture bhv of mycount is
signal b1,b2:integer range 0 to 9;
  begin
 p1:process(clk)----clock delay
    variable a:integer range 0 to 1000;
    begin
    s1<='0';
    s2<='0';
    if clk'event and clk='1'  then
      if a<1000 then a:=a+1;
      else a:=0;
        if b1<9 then b1<=b1+1;
        else b1<=0;
          if b2<9 then b2<=b2+1;
          else b2<=0;
          end if;
        end if;
      end if;
    end if;
end process;
p2:process(b1,b2)
   begin
  
   if b1=0 then y1<="0111111";
    elsif b1=1 then y1<="0000110";
    elsif b1=2 then y1<="1011011";
    elsif b1=3 then y1<="1001111";
    elsif b1=4 then y1<="1100110";
    elsif b1=5 then y1<="1101101";
    elsif b1=6 then y1<="1111101";
    elsif b1=7 then y1<="0000111";
    elsif b1=8 then y1<="1111111";
   else y1<="1101111"; 
       
   end if;
   end process;
p3:process(b2)
   begin
   if b2=0 then y2<="0111111";
    elsif b2=1 then y2<="0000110";
    elsif b2=2 then y2<="1011011";
    elsif b2=3 then y2<="1001111";
    elsif b2=4 then y2<="1100110";
    elsif b2=5 then y2<="1101101";
    elsif b2=6 then y2<="1111101";
    elsif b2=7 then y2<="0000111";
    elsif b2=8 then y2<="1111111";
   else y2<="1101111"; 
   end if;
   end process;
end bhv;