myled8.tan.rpt

led跑马灯显示

; N/A   ; None         ; 14.100 ns  ; b[0] ; y[4] ; clk        ;
; N/A   ; None         ; 14.100 ns  ; b[1] ; y[4] ; clk        ;
; N/A   ; None         ; 14.100 ns  ; b[2] ; y[5] ; clk        ;
; N/A   ; None         ; 14.100 ns  ; b[1] ; y[5] ; clk        ;
; N/A   ; None         ; 14.000 ns  ; b[2] ; y[4] ; clk        ;
; N/A   ; None         ; 14.000 ns  ; b[0] ; y[5] ; clk        ;
; N/A   ; None         ; 12.200 ns  ; b[0] ; y[6] ; clk        ;
; N/A   ; None         ; 12.200 ns  ; b[1] ; y[6] ; clk        ;
; N/A   ; None         ; 12.200 ns  ; b[2] ; y[7] ; clk        ;
; N/A   ; None         ; 12.200 ns  ; b[1] ; y[7] ; clk        ;
; N/A   ; None         ; 12.100 ns  ; b[2] ; y[6] ; clk        ;
; N/A   ; None         ; 12.100 ns  ; b[0] ; y[7] ; clk        ;
+-------+--------------+------------+------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Mar 23 15:50:23 2009
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off myled8 -c myled8
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 117.65 MHz between source register "lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10]" and destination register "b[1]" (period= 8.5 ns)
    Info: + Longest register to register delay is 7.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B14; Fanout = 4; REG Node = 'lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10]'
        Info: 2: + IC(1.200 ns) + CELL(1.600 ns) = 2.800 ns; Loc. = LC1_B13; Fanout = 1; COMB Node = 'LessThan~84'
        Info: 3: + IC(0.200 ns) + CELL(1.400 ns) = 4.400 ns; Loc. = LC4_B13; Fanout = 15; COMB Node = 'LessThan~46'
        Info: 4: + IC(0.200 ns) + CELL(1.400 ns) = 6.000 ns; Loc. = LC3_B13; Fanout = 3; COMB Node = 'b[0]~18'
        Info: 5: + IC(0.200 ns) + CELL(0.900 ns) = 7.100 ns; Loc. = LC2_B13; Fanout = 10; REG Node = 'b[1]'
        Info: Total cell delay = 5.300 ns ( 74.65 % )
        Info: Total interconnect delay = 1.800 ns ( 25.35 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.500 ns
            Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC2_B13; Fanout = 10; REG Node = 'b[1]'
            Info: Total cell delay = 2.200 ns ( 62.86 % )
            Info: Total interconnect delay = 1.300 ns ( 37.14 % )
        Info: - Longest clock path from clock "clk" to source register is 3.500 ns
            Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC5_B14; Fanout = 4; REG Node = 'lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[10]'
            Info: Total cell delay = 2.200 ns ( 62.86 % )
            Info: Total interconnect delay = 1.300 ns ( 37.14 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: tco from clock "clk" to destination pin "y[0]" through register "b[1]" is 14.700 ns
    Info: + Longest clock path from clock "clk" to source register is 3.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC2_B13; Fanout = 10; REG Node = 'b[1]'
        Info: Total cell delay = 2.200 ns ( 62.86 % )
        Info: Total interconnect delay = 1.300 ns ( 37.14 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Longest register to pin delay is 10.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B13; Fanout = 10; REG Node = 'b[1]'
        Info: 2: + IC(3.000 ns) + CELL(1.500 ns) = 4.500 ns; Loc. = LC5_F19; Fanout = 1; COMB Node = 'reduce_nor~8'
        Info: 3: + IC(1.100 ns) + CELL(4.900 ns) = 10.500 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'y[0]'
        Info: Total cell delay = 6.400 ns ( 60.95 % )
        Info: Total interconnect delay = 4.100 ns ( 39.05 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Mar 23 15:50:24 2009
    Info: Elapsed time: 00:00:01