📄 myled8.vhd
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entity myled8 is
port (clk:in bit;
y:out bit_vector(7 downto 0));
end myled8;
architecture bhv of myled8 is
signal b:integer range 0 to 7;
begin
a1:process(clk)
variable a:integer range 0 to 4000;
begin
if clk'event and clk='1' then
if a<4000 then
a:=a+1;
else a:=0;
b<=b+1;
end if;
end if;
end process;
a2:process(b)
begin
if b=0 then y<="00000001";
elsif b=1 then y<="00000010";
elsif b=2 then y<="00000100";
elsif b=3 then y<="00001000";
elsif b=4 then y<="00010000";
elsif b=5 then y<="00100000";
elsif b=6 then y<="01000000";
else y<="10000000";
end if;
end process;
end architecture;
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