jcanhcs12.c

在Freescale16位单片机MC9s12dp256上移植了J1939源码和操作系统（ucOSII）。

  bCanStatus &= ~CAN_STS_SLEEPING;
  //OS_EXIT_CRITICAL();
}
#pragma CODE_SEG DEFAULT_ROM

/*!
  Prepare a CAN buffer to handle a given remote message.
  \param ptMsg pointer to buffer
  \return NO_ERR buffer established
*/
BYTE gCan_PrepareRemoteMessage(CAN_MSG MEM_AREA *ptMsg)
{
  if (ptMsg == 0) {
    return NO_ERR;
  } /* if */
  return NO_ERR;
}


/*!
  Read the current status information of the CAN controller.
  The variable \e bCanStatus is local to the CAN module. Via this call
  we have an encapsulated access to this information.
  \return
  \link #CAN_STS_NORMAL CAN_STS_NORMAL \endlink
  or
  \link #CAN_STS_RESET CAN_STS_RESET \endlink
  | \link #CAN_STS_WARNING CAN_STS_WARNING \endlink
  | \link #CAN_STS_BUS_OFF CAN_STS_BUS_OFF \endlink
  | \link #CAN_STS_SLEEPING CAN_STS_SLEEPING \endlink
  | \link #CAN_STS_OVERRUN CAN_STS_OVERRUN \endlink
  | \link #CAN_STS_TX_OK CAN_STS_TX_OK \endlink
*/
BYTE gCan_GetCanStatus(void)
{
  if (TestBitValue(CAN_CTL0 + CAN_BASIC_ADR, CAN_FLAG_SYNCH)) {
    bCanStatus &= ~CAN_STS_BUS_OFF;
  } /* if */

  if ((ReadByte(CAN_RFLG + CAN_BASIC_ADR) & 0x0C) == 0) {
    bCanStatus &= ~CAN_STS_WARNING;
  } /* if */
  return bCanStatus;                       /* OUT: actual status           */
}


/*!
  This function signals that the first message (boot-up message) is transmitted
  successfully.
  \retval TRUE - First message successfully transmitted.
  \retval FALSE - First message not yet transmitted.
*/
BYTE gCan_TxOccurred(void) 
{
  return bFirstMsgTrans;
}

/*--------------------------------------------------------------------*/
/*  fuctions for MyCAN                                                     */
/*--------------------------------------------------------------------*/

/*!
  Set new mode of operation for MyCAN.

  \param bNewMode - new mode of operation
  \retval TRUE - new mode established
  \retval FALSE - new mode refused
*/
BYTE gMyCan_ActivateMode(BYTE bNewMode)
{
  BYTE bChangeOk = TRUE;

  switch (bNewMode) {
    case MODE_CONFIG:
      /* enable software initialization - reset request */
      WriteByte(CAN_CTL0 + MYCAN_BASIC_ADR, CAN_FLAG_INITRQ);
      while (!TestBitValue(CAN_CTL1 + MYCAN_BASIC_ADR, CAN_FLAG_INITAK));
      bCanStatus |= CAN_STS_RESET;
      break;

    case MODE_NORMAL:
      /* reset request finished */
      SetBitValue(CAN_CTL1 + MYCAN_BASIC_ADR, CAN_FLAG_CANE);
      ResetBitValue(CAN_CTL1 + MYCAN_BASIC_ADR, CAN_FLAG_LISTEN);
      WriteByte(CAN_CTL0 + MYCAN_BASIC_ADR, 0);
      while (TestBitValue(CAN_CTL1 + MYCAN_BASIC_ADR, CAN_FLAG_INITAK));
      bCanStatus &= ~CAN_STS_RESET;
      bCanStatus &= ~CAN_STS_SLEEPING;
      break;

    case MODE_SLEEP:
      /* controller in sleep mode */
      SetBitValue(CAN_CTL0 + MYCAN_BASIC_ADR, CAN_FLAG_SLPRQ);
      while (!TestBitValue(CAN_CTL1 + MYCAN_BASIC_ADR, CAN_FLAG_SLPAK));
      bCanStatus |= CAN_STS_SLEEPING;
      break;

    case MODE_LOOPBK:
      /* enable loop back self test mode */
      SetBitValue(CAN_CTL1 + MYCAN_BASIC_ADR, CAN_FLAG_LOOPB);
      break;

    case MODE_LISTEN:
      SetBitValue(CAN_CTL1 + MYCAN_BASIC_ADR, CAN_FLAG_LISTEN);
      break;

    default:
      bChangeOk = FALSE; /* unknown mode */
      break;
  } /* switch */
  return bChangeOk;
}


/*!
  Initialize the CAN controller.
  \param bIndex selects the bit timing
*/
void gMyCan_CntrlInit(BYTE bIndex)
{
  gMyCan_ActivateMode(MODE_CONFIG);

  /* set clock source */
  /* uncomment if necessary
  SetBitValue(CAN_CTL1 + MYCAN_BASIC_ADR, CAN_FLAG_CLKSRC);
  */

  /* set baud rate */
  WriteByte(CAN_BTR0 + MYCAN_BASIC_ADR, tCCanBtr[bIndex][0]);
  WriteByte(CAN_BTR1 + MYCAN_BASIC_ADR, tCCanBtr[bIndex][1]);

  /* set acceptance registers */
  WriteByte(CAN_IDAC + MYCAN_BASIC_ADR, 0);
  WriteByte(CAN_IDAR0 + MYCAN_BASIC_ADR, CAN_CODE0);
  WriteByte(CAN_IDAR1 + MYCAN_BASIC_ADR, CAN_CODE1);
  WriteByte(CAN_IDAR2 + MYCAN_BASIC_ADR, CAN_CODE2);
  WriteByte(CAN_IDAR3 + MYCAN_BASIC_ADR, CAN_CODE3);
  WriteByte(CAN_IDMR0 + MYCAN_BASIC_ADR, CAN_MASK0);
  WriteByte(CAN_IDMR1 + MYCAN_BASIC_ADR, CAN_MASK1);
  WriteByte(CAN_IDMR2 + MYCAN_BASIC_ADR, CAN_MASK2);
  WriteByte(CAN_IDMR3 + MYCAN_BASIC_ADR, CAN_MASK3);

  gMyCan_ActivateMode(MODE_NORMAL); 
  
 // gMyCan_ActivateMode(MODE_NORMAL); 

  Can_Configure();

  /* enable receive interrupts */
  WriteByte(CAN_RIER + MYCAN_BASIC_ADR, 
            CAN_FLAG_WUPIE
            | CAN_FLAG_CSCIE
            | CAN_FLAG_RSTATE1
            | CAN_FLAG_TSTATE1
            | CAN_FLAG_OVRIE
            | CAN_FLAG_RXFIE);

  /* enable transmit interrupts */
  WriteByte(CAN_TIER + MYCAN_BASIC_ADR, CAN_FLAG_TXEIE0);

  /* enable transmit buffer 0 */
  WriteByte(CAN_TBSEL + MYCAN_BASIC_ADR, CAN_FLAG_TX0);

  bMyISRInitiated = TRUE;
}


/*!
  \brief CAN transmit ISR for MyCAN to BECU.

  The CAN transmit interrupt service routine.
*/
#pragma CODE_SEG NON_BANKED

#ifdef COSMIC12
@interrupt void
#endif /* COSMIC12 */
//#ifdef __MWERKS__
#pragma TRAP_PROC
# if MYCAN_BASIC_ADR == CAN_0_ADR
void interrupt 39
# elif MYCAN_BASIC_ADR == CAN_1_ADR
void interrupt 43
# elif MYCAN_BASIC_ADR == CAN_2_ADR
void interrupt 47
# elif MYCAN_BASIC_ADR == CAN_3_ADR
void interrupt 51
# elif MYCAN_BASIC_ADR == CAN_4_ADR
void interrupt 55
# endif
//#endif /* __MWERKS__ */
gMYCan_TxIntHandler(void)
{
// #if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register     */
   //  OS_CPU_SR  cpu_sr;
 //#endif
 // OS_ENTER_CRITICAL();
  
  /* disable transmit interrupt */
  ResetBitValue(CAN_TIER + MYCAN_BASIC_ADR, CAN_FLAG_TXEIE0);

  /* transmit interrupt - last transmission successful */
 // bFirstMsgTrans = TRUE;
 // bCanStatus |= CAN_STS_TX_OK;

  /* signal empty TX buffer */
  gCB_SignalTx();
 // OS_EXIT_CRITICAL();
  
}

/*!
  \brief CAN receive ISR for MyCAN.

  The CAN receive interrupt service routine.
*/
#ifdef COSMIC12
@interrupt void
#endif /* COSMIC12 */
//#ifdef __MWERKS__
#pragma TRAP_PROC
# if MYCAN_BASIC_ADR == CAN_0_ADR
void interrupt 38
# elif MYCAN_BASIC_ADR == CAN_1_ADR
void interrupt 42
# elif MYCAN_BASIC_ADR == CAN_2_ADR
void interrupt 46
# elif MYCAN_BASIC_ADR == CAN_3_ADR
void interrupt 50
# elif MYCAN_BASIC_ADR == CAN_4_ADR
void interrupt 54
# endif
//#endif /* __MWERKS__ */
gMyCan_RxIntHandler(void)
{
BYTE MessDataIndex;
//#if OS_CRITICAL_METHOD == 3                                /* Allocate storage for CPU status register     */
    //OS_CPU_SR  cpu_sr;
//#endif
#if ID_FILTER != 0
  WBYTE wId;                        /* received identifier              */
#endif /* ID_FILTER */
//OS_ENTER_CRITICAL();

#if ID_FILTER != 0
  /* 29 bit identifier not allowed */
  if (TestBitValue(CAN_IDR1 + CAN_RX_BUF + MYCAN_BASIC_ADR, 0x08)) {
    /* release receive buffer */
    WriteByte(CAN_RFLG + MYCAN_BASIC_ADR, CAN_FLAG_RXF);
    return;
    //goto ISROut;
  } /* if */

  /* get identifier */
  wId.bc.lb = (ReadByte(CAN_IDR0 + CAN_RX_BUF + MYCAN_BASIC_ADR) << 3)
            | (ReadByte(CAN_IDR1 + CAN_RX_BUF + MYCAN_BASIC_ADR) >> 5);
  wId.bc.mb = ReadByte(CAN_IDR0 + CAN_RX_BUF + MYCAN_BASIC_ADR) >> 5;

  /* check identifier */
  if (gCB_PreCheckXtdId(wId.wc) == FALSE) {
    /* release receive buffer */
    WriteByte(CAN_RFLG + MYCAN_BASIC_ADR, CAN_FLAG_RXF);
    return;
    //goto ISROut;
  } /* if */

  /* standard frame received */
  stCanMsgBuffer.Ext = 0;

  /* copy COB ID */
  stCanMsgBuffer.qbId.fb.b0 = wId.bc.lb;
  stCanMsgBuffer.qbId.fb.b1 = wId.bc.mb;
  stCanMsgBuffer.qbId.fb.b2 = 0;
  stCanMsgBuffer.qbId.fb.b3 = 0;

  /* get RTR */
  stCanMsgBuffer.Rtr = (ReadByte(CAN_IDR1 + CAN_RX_BUF + MYCAN_BASIC_ADR) & 0x10) >> 4;
#else
  /* check 29 bit identifier */
  if (TestBitValue(CAN_IDR1 + CAN_RX_BUF + MYCAN_BASIC_ADR, 0x08)) {
    /* extended frame received */
    stCanMsgBuffer.Ext = 1;

    /* get COB ID */
    stCanMsgBuffer.qbId.fb.b0 = (ReadByte(CAN_IDR2 + CAN_RX_BUF + MYCAN_BASIC_ADR) << 7)
                              | (ReadByte(CAN_IDR3 + CAN_RX_BUF + MYCAN_BASIC_ADR) >> 1);
    stCanMsgBuffer.qbId.fb.b1 = (ReadByte(CAN_IDR1 + CAN_RX_BUF + MYCAN_BASIC_ADR) << 7)
                              | (ReadByte(CAN_IDR2 + CAN_RX_BUF + MYCAN_BASIC_ADR) >> 1);
    stCanMsgBuffer.qbId.fb.b2 = (ReadByte(CAN_IDR0 + CAN_RX_BUF + MYCAN_BASIC_ADR) << 5)
                              | ((ReadByte(CAN_IDR1 + CAN_RX_BUF + MYCAN_BASIC_ADR) >> 3) & 0x1C)
                              | ((ReadByte(CAN_IDR1 + CAN_RX_BUF + MYCAN_BASIC_ADR) >> 1) & 0x03);
    stCanMsgBuffer.qbId.fb.b3 = ReadByte(CAN_IDR0 + CAN_RX_BUF + MYCAN_BASIC_ADR) >> 3;

    if(gCB_PreCheckXtdId(stCanMsgBuffer.qbId.dw) == FALSE)
	{
      /* release receive buffer */
      WriteByte(CAN_RFLG + MYCAN_BASIC_ADR, CAN_FLAG_RXF);
      return;
      //goto ISROut;	
	} /* if */

    /* get RTR */
    stCanMsgBuffer.Rtr = ReadByte(CAN_IDR3 + CAN_RX_BUF + MYCAN_BASIC_ADR) & 0x01;
  } /* if */
  else {
    /* standard frame received */
    stCanMsgBuffer.Ext = 0;

    /* get COB ID */
    stCanMsgBuffer.qbId.fb.b0 = (ReadByte(CAN_IDR0 + CAN_RX_BUF + MYCAN_BASIC_ADR) << 3)
                              | (ReadByte(CAN_IDR1 + CAN_RX_BUF + MYCAN_BASIC_ADR) >> 5);
    stCanMsgBuffer.qbId.fb.b1 = ReadByte(CAN_IDR0 + CAN_RX_BUF + MYCAN_BASIC_ADR) >> 5;
    stCanMsgBuffer.qbId.fb.b2 = 0;
    stCanMsgBuffer.qbId.fb.b3 = 0;

    /* get RTR */
    stCanMsgBuffer.Rtr = (ReadByte(CAN_IDR1 + CAN_RX_BUF + MYCAN_BASIC_ADR) & 0x10) >> 4;
  } /* else */
#endif /* ID_FILTER */

  /* get DLC */
  stCanMsgBuffer.Dlc = ReadByte(CAN_DLR + CAN_RX_BUF + MYCAN_BASIC_ADR) & 0x0F;
    
  /* check DLC */
  if (stCanMsgBuffer.Dlc > 8) {
    stCanMsgBuffer.Dlc = 8;
  } /* if */
    
  /* copy message data bytes */
  for (MessDataIndex = 0; MessDataIndex < stCanMsgBuffer.Dlc; MessDataIndex++) {
    stCanMsgBuffer.bDb[MessDataIndex] = ReadByte(CAN_DSR0 + CAN_RX_BUF + MessDataIndex + MYCAN_BASIC_ADR);
  } /* for */

  /* release receive buffer */
  WriteByte(CAN_RFLG + MYCAN_BASIC_ADR, CAN_FLAG_RXF);

  /* put message to storage location */
  gCB_CanBufferMsg(&stCanMsgBuffer);
  
  //ISROut:OS_EXIT_CRITICAL();
  
  
}

#pragma CODE_SEG DEFAULT_ROM


/*--------------------------------------------------------------------*/
/*  documentation                                                     */
/*--------------------------------------------------------------------*/

/*!
  \file
  \brief CAN driver for the msCAN12 Rev. 2.08.
  \par File name \$Workfile: canhcs12.c $
  \version \$Revision: 2 $
  \date \$Date: 5.06.03 8:14 $
  \author (c) 1998-2003 by Vector Informatik GmbH, Stuttgart
*/

/*!
  \var tCCanBtr
  \brief CAN controller bit timing values.

  The bit timing values are defined for a 16 MHz clock in ascending order,
  first BTR0 then BTR1.
  - 10K bit/s
  - 20K bit/s
  - 50K bit/s
  - 100K bit/s
  - 125K bit/s
  - 250K bit/s
  - 500K bit/s
  - 800K bit/s
  - 1M bit/s
*/