vpr_5.txt

VPR布局布线源码

          each pin connects (fractional). Note: type absolute or fractional for Fc_in and Fc_out must be 
          the same. Full disregards whether it is fractional or absolute and can be used in either case. 

     <fc_out type="{frac|abs|full}">{<int> | <float>}</fc_out> 

    Content: 
    Sets the number of tracks to which each logic block output pin connects in each channel 
    bordering the pin. 
    Type attribute is the same as described above in Fc_in 

<pinclasses> 
    Contains a group of pin classes in the form of <class> tags. A <class> tag is defined as: 

<class type="{in|out|global}">(<int> )*</class> 

    Where * represents a Kleene star and brackets for regular expression grouping only (Do not 
    put brackets in the architecture file). The type attribute specifies if pin numbers specified for 
    this class are inputs, outputs, or global. All pins with the same class number are logically 
    equivalent -- such as all the inputs of a LUT. Class numbers must start at zero and be 
    consecutive. The global keyword is optional; if specified, it comes after the class number. 
    Global input pins can connect only to signals marked as global in the netlist (typically clocks). 
    Global input pins are not connected into the normal routing; it is assumed they connect to a 
    special, dedicate resource used for special nets like clocks. 
    NOTE: The order in which your inpin and outpin statements appear must be the same as the 
    order in which your netlist (.net) file lists the connections to the clbs. For example, if the first pin 
    on each clb in the netlist file is the clock pin, your first pin statement in the architecture file must 
    be an inpin statement defining the clock pin. 
    Pads are always assumed to have only one pin (either an input or an output), and this pin is 
    accessible from the one channel bordering that pad. Hence no inpin or outpin statements are 
    given for pads. 


    Declares an input pin, determines the class to which this pin belongs, and sets the side(s) of 
    CLBs on which the physical output pin connection(s) is (are). 


<pinlocations> 
    Contains a group of pin locations in the form of <loc> tags. A <loc> tag is defined as: 

<loc side="{left|right|bottom|top}" offset=”<int>”><int>*</class> 

    Where * represents a Kleene star and brackets for regular expression grouping only (Do not 
    put brackets in the architecture file). The side attribute specifies which of the four directions 
    the pins in the contents are located on and offset attribute specifies the grid distance from the 
    bottom grid tile that the pin is specified for. Pins on the bottom grid tile does not have an offset 
    attribute. The offset value must be less than the height of the functional block. A functional 
    block may not contain pins inside of itself. 


    Physical equivalence is specified by listing a pin number more than once for different locations. 


<gridlocations> 
    Specifies the columns on the FPGA that will consist of this functional block. The columns are 
    specified by a group of <loc> tags and there are three ways to use this tag: 

<loc type="col" start="<int>" repeat="<int>" priority="<int>"/> 

    This specifies an absolute column assignment. The first column to contain this functional block 
    is specified in start. Every column that satisfies x = start_x + k*repeat, where k is any integer, 
    will be composed of this functional block. 

<loc type="rel" pos="0.5"             priority="<int>"/> 

    This specifies a single column to be composed of this functional block where the column is 
    specified as a fraction of the width. 

<loc type="fill" priority="1"/> 

    This is a special specification such that all unspecified columns get assigned this functional 
    block. 


    For all three <loc> tags, the priority attribute is used to resolve collisions when two different 
    functional block is supposed to use the same column. The larger integer specified for priority 
    gets the location. 


<timing>content</timing> 
    Optional. This timing is specifically for the paths from the functional blocks to the subblocks. 
    The content for this tag specifies timing and is used and must be specified for timing analysis. 

<tedge type”{ T_sblk_opin_tosblk_ipin | T_fb_ipin_to_sblk_ipin | 
T_sblk_opin_to_fb_opin}”>float</tedge> 
    This tag tedge describes a timing edge for each of the three possibilities: 
             T_sblk_opin_to_fb_opin – Delay from the output of a subblock to a clb (logic block) 
             output pin. For architectures without local routing (e.g. the output of a LUT is 
             hardwired to each logic block output), this delay is essentially zero. 
             T_fb_ipin_to_sblk_ipin – Delay from an input pin of a clb (logic block) to an input pin of 
             a subblock within that clb. For architectures without local routing (i.e. clb input pins 
             connect directly to some logic element, like a LUT or multiplexer) this delay is 
             essentially zero. 
             T_sblk_opin_to_sblk_ipin - Delay from the output of a subblock to the input of another 
             subblock within the same clb. For architectures without local routing (e.g. the output 
             of one subblock is hard- wired to the input of another) this delay is essentially zero. 
    All three must be included for timing analysis. 




<subblocks max_subblocks=”int” max_subblock_inputs=”int”>content</subblocks> 
    Contains the information for the subblocks of a functional block. 


    Max_subblocks describes how many subblocks there are (in the case of clbs, this is N), and 
    max_subblock_inputs describes the number of inputs per subblocks (in the case of clbs, this is 
    K). For something like a multiplier, we would expect the number of subblocks to be 1 and the 

         number of input pins to match that of the functional block. 


         The content of subblocks contains timing information for each subblock. However, the timing 
         information can only be specified such that all subblocks have the same timing characteristics 
         (meaning only one timing can be provided). The content is described in the next table. 


     The content within subblocks of a functional block is described in the table below. Note 
that there are three types of timing (one for the chip, one for the paths between functional 
blocks and subblocks, and one for internal subblock paths).               The timing described next is for 
internal subblock paths between inputs and outputs. 

     <timing>content</timing> 
         Optional. This timing is specifically to be embedded in the subblocks content. The content for 
         this tag specifies timing and is used and must be specified for timing analysis.       This content 
         consists of T_comb, T_seq_in and T_seq_out as explained below 

     <T_comb> 
         The delay from any subblock input to the subblock output when this subblock is used in 
         combinational mode.       A subblock is used in combinational mode when the netlist leaves its 
         clock pin OPEN. 


         This describes the timing characteristic for all inputs to all outputs of the subblock. Each input 
         within the subblock will have an associated <trow> (as described below) in which a timing 
         number is provided for the time of the combinational input from this input to the collumn 
         ordered outputs of the subblock. The trows are listed in sequential order from the first input to 
         the last input (row ordered). 


         This represents a matrix that describes the timing characteristics between all inputs and 
         outputs of the subblock. 

     <T_seq_in> 
         The delay from any subblock input pin to the FF storage element when this subblock is used in 
         sequential mode. A subblock is used in sequential mode when the netlist hooks its clock pin to 
         some signal. If this subblock was a simple flip flop, for example, then T_seq_in is the setup 
         time. If this subblock corresponds to, say, a LUT feeding into a flip flop, then T_seq_in should 
         be set to the LUT delay plus the setup time. Each entry is a <trow> (as described below) which 
         describes the timing for an output from the first output pin to the last output pin. 

     <T_seq_out> 
         The delay from the subblock storage element (FF) to the subblock output pin when this block is 
         used in sequential mode. A subblock is used in sequential mode when the netlist hooks its 
         clock pin to some signal. If this subblock had a flip flop hooked to its output pin, for example, 
         then T_seq_out would be the clock-to-Q delay of the flip flop. Each entry is a <trow> (as 
         described below) which describes the timing for an output from the first output pin to the last 
         output pin. 

     <trow>float</trow> 
         A timing container that when nested between: 
                  T_comb – specifies the timing between an input pin and collumn ordered outputs of a 
                  subblock 
                  T_seq_in – specifies the timing charactersitc of the sequential input (JASON) 
                  T_seq_out – specifies the timing characteristic of the sequential output (JASON) 


     One special case in the <typelist> is the input/output pads.                 They have the following 
settings. 

   <io capacity=”int” t_inpad=”float” t_outpad=”float”>content</io> 
       This contains the details for the input and output pads around the periphery of the chip. The 
       following attributes are specified: 
                capacity is the number of I/Os that are contained per io pad. This means that multiple 
                ios can be contained in one io pad. 
                t_inpad is the delay through an input pad. 
                t_outpad is the delay through an output pad. 

   <fc_in type="{frac|abs|full}">{<int> | <float>}</fc_in> 
       Content: 
       Sets the number of tracks to which each logic block input pin connects in each channel 
       bordering the pin. The Fc value used is always the minimum of the specified Fc and the 
       channel width, W. It is best to set the type attribute to full if you want Fc to always be W. 
       type attribute: 
       The type attribute indicates whether the Fc [12] value should be interpreted as the number of 
       tracks to which each pin connects (absolute), or the fraction of tracks in a channel to which 
       each pin connects (fractional). Note: type absolute or fractional for Fc_in and Fc_out must be 
       the same. Full disregards whether it is fractional or absolute and can be used in either case. 

   <fc_out type="{frac|abs|full}">{<int> | <float>}</fc_out> 
       Content: 
       Sets the number of tracks to which each logic block output pin connects in each channel 
       bordering the pin. 
       Type attribute is the same as described above in Fc_in 



6.2.3 Description of the Wire Segments 

   The content within the <segmentlist> tag consists of a group of <segment> tags. The 
<segment> tag and its contents are described in the table below. 

   <segment length=”int” type=”{bidir|unidir}” freq=”float” Rmetal=”float” 
   Cmetal=”float”>content</segment> 
       Describes the properties of a segment 


       length: Either the number of logic blocks spanned by each segment, or the keyword longline. 
       Longline means segments of this type span the entire FPGA array. 

       freq: The supply of routing tracks composed of this type of segment. VPR automatically 
       determines the percentage of tracks for each segment type by taking the frequency for the type 
       specified and dividing with the sum of all frequencies.         It is recommended that the sum of all 
       segment frequencies be in the range 1 to 100. 

       Rmetal:    Resistance per unit length (in terms of logic blocks) of this wiring track, in Ohms. For 
       example, a segment of length 5 with Rmetal = 10 Ohms / logic block would have an end-to-end 
       resistance of 50 Ohms. 

       Cmetal: Capacitance per unit length (in terms of logic blocks) of this wiring track, in Farads. For 
       example, a segment of length 5 with Cmetal = 2e-14 F / logic block would have a total metal 
       capacitance of 10e-13F. 

       directionality: This is either uni_directional or bi_directional and indicates whether a segment 
       has multiple drive points (bi_directional), or a single driver at one end of the wire segment 
       (uni_directional). All segments must have the same directionality value. See [15] for a description 
       of uni-directional single-driver wire segments. 

       Content contains the switch names and the depopulation pattern as described below. 

   <sb type=”pattern”>int list</sb> 
       This tag describes the switch block depopulation (as illustrated in the figure below) for this 
       particular wire segment. For example, the firsth length 6 wire in the figure below has an sb 
       pattern of “1 0 1 0 1 0 1”. The second wire has a pattern of “0 1 0 1 0 1 0”. A “1” indicates the 
       existance of a switch block and a “0” indicates that there is no switch box at that point.