vpr_5.txt

VPR布局布线源码

.output out_and2                              #Output pad. 
        pinlist: and2 


     In the netlist above the subblock line adds no new information -- since the logic block only 
contains one BLE, which pins are hooked to this BLE is obvious. Consider a netlist in which 

each logic block is a cluster-based logic block containing two subblocks, or BLEs, and let there 
also be a multiplier block: 

.input a 
       pinlist: a 

.input bpad 
       pinlist: b 

.input c 
       pinlist: c 

.input d 
       pinlist: d 

.input clk 
       pinlist: clk 

.global clk # Typical case: clock needn’t be routed, as there’s a 
                       # special network for it. 

# Example logic block: 4 inputs, 2 outputs, 1 clock. 
# Internally, the logic block contains two BLEs, 
# each of which consists of a 3-LUT and a FF. 
# Local routing allows subblock outputs to connect to subblock inputs 
# in the same logic block. 

.clb more_complex 
       pinlist: a b c open out_1 out_2 clk 
       subblock: sb_zero 0 1 open 4 open             # BLE inputs are a and b, output 
                                                    # goes to out_1. Output isn’t 
                                                    # registered. 
       subblock: sb_one ble_0 1 2 5 6                # BLE inputs are the output of 
                                                    # subblock 0, 
                                                 # and nets b and c. The output 
                                                 # goes to out_2. 
                                                 # The output is registered. 
.mult two_by_two 
       pinlist:       a b c d out_3 out_4 out_5 out_6 open # Combinational 2x2 
                                                                  # multiply with 4 
                                                                  #inputs and 4 outputs 
       subblock: sb_zero 0 1 2 3 4 5 open             # BLE inputs are a, b, c, d 
                                                      #outputs are out_3, out_4, out_5, 
                                                      # and out_6.      Outputs are not 
                                                     # registered. 

.output opad_1 
       pinlist: out_1 

.output opad_2 
       pinlist: out_2 

.output opad_3 
       pinlist: out_3 

.output opad_4 
       pinlist: out_4 

.output opad_5 
       pinlist: out_5 

.output opad_6 
        pinlist: out_6 




     In the netlist above, one needs the subblock statements to know what connections are 
made internally to the logic block by local routing. Figure 4 shows the connections this netlist 
describes for the clb “more_complex” only. Note also that while the subblock lines describe the 
internal structure of the clb in terms of BLEs, the BLE structure is general enough that the 
timing behaviour of essentially arbitrary logic blocks can be described in terms of subblock 
lines. VPR needs the subblock information in a netlist only for timing analysis. 




6.2      FPGA Architecture File (.xml) Format 

     The architecture file is specified in xml format. It is composed of a hierarchy of start and 
end tags with optional attributes and content inside each tag giving additional information. As a 
convention, curly brackets {…} represents an option with each option separated by |.                       For 
example, a={1 | 2 | open} means field “a” can take a value of 1, 2, or open. 
     The first tag in all architecture files is the <architecture> tag.                This tag contains all 
other tags in the architecture file.         The architecture tag contains five other tags.           They are 
<layout> <device>, <switchlist>, <segmentlist>, and <typelist>. 

     <layout {auto=”float” | width=”int” height=” int”}/> 
         This tag specifies the size and shape of the FPGA in grid units. The keyword auto indicates 
         that the size should be chosen to be the minimal dimensions that fits the given circuit. The size 
         is determined from the number grid tiles used by the circuit as well as the number of IO pins 
         that it uses. The aspect ratio of the FPGA is given after the auto keyword and is the ratio 
         width/height. 
         Alternately, the size can be explicitly given as the size in the x direction (width) followed by the 
         size in the y direction (height). 

     <device>content</device> 
         Content inside this tag specifies device information.      It contains the tags <sizing>, <timing>, 
         <area>, <chan_width_distr>, and <switch_block>. 

     <switchlist>content</switchlist> 
         Content inside this tag contains a group of <switch> tags that specify the types of switches and 
         their properties. 

     <segmentlist>content</segmentlist> 
         Content inside this tag contains a group of <segment> tags that specify the types of wire 
         segments and their properties. 

   < typelist>content</ typelist> 
       Content inside this tag contains a group of <type> tags that specify the types of functional 
       blocks and their properties. 




6.2.1 Description of Device Information in the FPGA 

   The tags within the device tag are described in the following table. 

   <sizing R_minW_nmos="float" R_minW_pmos="float" ipin_mux_trans_size="int"/> 
       Specifies parameters used by the area model built into VPR 
       R_minW_nmos attribute: 
       The resistance of minimum-width nmos transistor. This data is used only by the area model 
       built into VPR. 
       R_minW_pmos attribute: 
       The resistance of minimum-width pmos transistor. This data is used only by the area model 
       built into VPR. 
       ipin_mux_trans_size attribute: 
       This specifies the size of each transistor in the ipin muxes. Given in minimum transistor units. 
       The mux is implemented as a two-level mux.). 

   <timing C_ipin_cblock="float" T_ipin_cblock="float"/> 
       Optional. Attributes specify timing information general to the device and must be specified for 
       timing analysis. 
       C_ipin_cblock attribute: 
       Input capacitance of the buffer isolating a routing track from the connection boxes 
       (multiplexers) that select the signal to be connected to an logic block input pin. One of these 
       buffers is inserted in the FPGA for each track at each location at which it connects to a 
       connection box. For example, a routing segment that spans three logic blocks, and connects 
       to logic blocks at two of these three possible locations would have two isolation buffers 
       attached to it. If a routing track connects to the logic blocks both above and below it at some 
       point, only one isolation buffer is inserted at that point. If your connection from routing track to 
       connection block does not include a buffer, set this parameter to the capacitive loading a track 
       would see at each point where it connects to a logic block or blocks. 
       T_ipin_cblock attribute: 
       Delay to go from a routing track, through the isolation buffer (if your architecture contains 
       these) and a connection block (typically a multiplexer) to a logic block input pin. 




   <area grid_logic_tile_area="float"/> 

         Used for an area estimate of the amount of area taken by all the functional blocks. 

    <switch_block type="{wilton|subset|universal}" fs="int"/> 
         C When using bidirectional segments, all the switch blocks [12] have Fs = 3. That is, whenever 
         horizontal and vertical channels intersect, each wire segment can connect to three other wire 
         segments. The exact topology of which wire segment connects to which can be one of three 
         choices. The subset switch box is the planar or domain-based switch box used in the Xilinx 
         4000 FPGAs -- a wire segment in track 0 can only connect to other wire segments in track 0 
         and so on. The wilton switch box is described in [13], while the universal switch box is 
         described in [14]. To see the topology of a switch box, simply hit the “Toggle RR” button when 
         a completed routing is on screen in VPR. In general the wilton switch box is the best of these 
         three topologies and leads to the most routable FPGAs. 
         When using unidirectional segments, a modified wilton switch block pattern is used regardless 
         of the specified switch_block_type. 

    <chan_width_distr>content</chan_width_distr> 
         Content inside this tag is described in the next table 



    If global routing is to be performed, channels in different directions and in different parts of 
the FPGA can be set to different relative widths. This is specified in the content within the 
<chan_width_distr> tag. If detailed routing is to be performed, however, all the channels in the 
FPGA must have the same width. 

    <io width= “float”/> 
         Width of the channels between the pads and core relative to the widest core channel. 

    <x distr=”{gaussian|uniform|pulse|delta}” peak=”float” width=” float” xpeak=” float” dc=” 
    float”/> 
         (Unknown if works properly) 
         The italicized quantities are needed only for pulse, gaussian, and delta (which doesn’t need 
         width). Most values are from 0 to 1. Sets the distribution of tracks for the x-directed channels -- 
         the channels that run horizontally. 
         If uniform is specified, you simply specify one argument, peak. This value (by convention 
         between 0 and 1) sets the width of the x-directed core channels relative to the y-directed 
         channels and the channels between the pads and core. Figure should make the specification 
         of uniform (dashed line) and pulse (solid line) channel widths more clear. The gaussian 
         keyword takes the same four parameters as the pulse keyword, and they are all interpreted in 
         exactly the same manner except that in the gaussian case width is the standard deviation of 
         the function. 

          The delta function is used to specify a channel width distribution in which all the channels have 
          the same width except one. The syntax is chan_width_x delta peak xpeak dc. Peak is the extra 
          width of the single wide channel. Xpeak is between 0 and 1 and specifies the location within the 
          FPGA of the extra-wide channel -- it is the fractional distance across the FPGA at which this 
          extra-wide channel lies. Finally, dc specifies the width of all the other channels. For example, 
          the statement chan_width_x delta 3 0.5 1 specifies that the horizontal channel in the middle of 
          the FPGA is four times as wide as the other channels. 
          Examples: 
          <x distr=”uniform” peak=”1”/> 
          <x distr=”gaussian” width=”0.5” peak=”0.8” xpeak=”0.6” dc=”0.2”/> 

     <y distr=”{gaussian|uniform|pulse|delta}” peak=” float” width=” float” xpeak=” float” dc=” 
     float”/> 
          Sets the distribution of tracks for the y-directed channels. 



6.2.2 Description of Functional Blocks in FPGA 

     The content within the <typelist> tag consists of a group of <type> tags. Each <type 
name="<string>" height="<int>"> tag describes a functional block. The name attribute 
is the name for the functional block and correspond exactly with the name for the block in the 
netlist. It is of the format .[name]; for example, .clb. The height attribute specifies how many 
grid tiles the functional block takes up. The <type> tag contains tags specified in the following 
table. 

     <fc_in type="{frac|abs|full}">{<int> | <float>}</fc_in> 
          Content: 
          Sets the number of tracks to which each logic block input pin connects in each channel 
          bordering the pin. The Fc value used is always the minimum of the specified Fc and the 
          channel width, W. It is best to set the type attribute to full if you want Fc to always be W. 
          type attribute: 
          The type attribute indicates whether the Fc [12] value should be interpreted as the number of 
          tracks to which each pin connects (absolute), or the fraction of tracks in a channel to which