vpr_5.txt

VPR布局布线源码

        Default: lut_size * cluster_size. 

   -clocks_per_cluster <int> 
        Number of distinct clocks in a logic cluster. 
        Default: 1. 

   -muxes_to_cluster_output_pins {on | off} 
        If “off”, each BLE output is hooked directly to a cluster output pin. If “on”, a set of N (one per 
        cluster output) N:1 multiplexers allows each output pin to be driven by any of the N BLEs within 
        a cluster. 
        Default: off. 


4.1.3 CAD Optimization Options 

   -timing_driven {on | off} 
        Controls whether the clustering algorithm attempts to optimize circuit timing by attempting to 
        capture critical connections within a logic cluster. 
        Default: on. 

   -connection_driven {on | off} 
        Controls whether or not T-VPack attempts to absorb, within one cluster, connections from the 
        output of one BLE to the input of another. 
        Default: off. 

   -hill_climbing {on | off} 
        Controls whether the algorithm used to pack BLEs into clusters allows hill climbing or is strictly 
        greedy. 
        Default: on. 

   -cluster_seed {timing | max_inputs} 
        Specifies the way in which the cluster packing algorithm picks the first BLE to be placed in an 
        empty cluster. Max_inputs picks the BLE with the most used inputs, while timing picks the BLE 
        on the most critical path. 
        Default: timing if timing_driven is on, max_inputs otherwise. 

   -allow_unrelated_clustering {on | off} 
        Controls whether or not BLEs with no attraction to the current cluster can be packed into it. 
        Default: on. 

   -alpha <float> 
        A tradeoff parameter that controls the optimization of delay in packing vs. the optimization of 
        signal sharing. A value of 0 focuses solely on signal sharing, while a value of 1 focuses solely 
        on timing. This option is meaningful only when timing_driven is on. 
        Default: 0.75. 

   -recompute_timing_after <int> 
        T-VPack will recompute its estimate of how timing-critical each connection is after packing the 
        specified number of BLEs into clusters. This option is meaningful only when timing_driven is 
        on. 
        Default: 32 000. 

   -block_delay <float> 

     The relative delay of a BLE. This option is meaningful only when timing_driven is on. 
     Default: 0.1. 

-intra_cluster_net_delay <float> 
     The relative delay of a signal that goes from one BLE to another using the local routing within a 
     cluster. This option is meaningful only when timing_driven is on. 
     Default: 0.1. 

-inter_cluster_net_delay <float> 
     The relative delay of a signal that goes from one BLE to another BLE that is in a different 
     cluster, or an IO pad. This option is meaningful only when timing_driven is on. 
     Default: 1.0. 

-allow_early_exit {on | off} 
     If on, the clusterer will stop re-timing analyzing a circuit once it believes the current, partially 
     complete packing, has fixed (“locked”) the critical path. 
     Default off. 

5.        Operation of VPR 

     Invoke VPR by typing: 

> vpr input.net input.arch placement.p output.routing [-options] 


     This section outlines how VPR’s graphics and options work; Section describes the format 
of each of the four files used by VPR. 

5.1       Graphics 

     The graphics included in VPR are very easy to use. Click any mouse button on the arrow 
keys to pan the view, or click on the Zoom-In, Zoom-Out and Zoom-Fit keys to zoom the view. 
Click on the Window button, then on the diagonally opposite corners of a box, to zoom in on a 
particular area. Selecting PostScript creates a PostScript file (in pic1.ps, pic2.ps, etc.) of the 
image on screen. Proceed tells VPR to continue with the next step in placing and routing the 
circuit, while Exit aborts the program. The menu buttons will be greyed out to show they are not 
selectable when VPR is working, rather than interactively displaying graphics. 
     The Toggle Nets button toggles the nets in the circuit visible/invisible. When a placement 
is being displayed, routing information is not yet known so nets are simply drawn as a “star;” 
that is, a straight line is drawn from the net source to each of its sinks. Click on any clb in the 
display, and it will be highlighted in green, while its fanin and fanout are highlighted in blue and 
red, respectively. Once a circuit has been routed the true path of each net will be shown. 
Again, you can click on Toggle Nets to make net routings visible or invisible, and clicking on a 
clb or pad will highlight their fanins and fanouts. 
     When a routing is on-screen, clicking on Toggle RR will switch between various views of 
the routing resources available in the FPGA. Wiring segments and clb pins are drawn in black, 
connections from wiring segments to input pins are shown in blue, connections from output pins 
to wiring segments are shown in red, and connections between wiring segments are shown in 
green. The points at which wiring segments connect to clb pins (connection box switches) are 
marked with an “X”. Switch box connections will have buffers (triangles) or pass transistors 
(circles) drawn on top of them, depending on the type of switch each connection uses. Clicking 
on a clb or pad will overlay the routing of all nets connected to that block on top of the drawing 
of the FPGA routing resources, and will label each of the pins on that block with its pin number. 
The routing resource view can be very useful in ensuring that you have correctly described your 
FPGA in the architecture description file -- if you see switches where they shouldn’t be or pins 
on the wrong side of a clb, your architecture description needs to be revised. 
     When a routing is shown on-screen, clicking on the Congestion button will show any 
overused routing resources (wires or pins) in red, if any overused resources exist. Finally, 
when a routing is on screen you can click on the Crit. Path button to see each of the nets on 
the critical path in turn. The current net on the critical path is highlighted in cyan; its source 
block is shown in yellow and the critical sink is shown in green. 
     NOTE: For this release, a few of the less common options are not fully tested and so are 
not necessarily working properly. As well, the –nx –ny and –aspect_ratio options are now part 
of the architecture file. The options not debugged are: 
                 num_regions 
                 base_cost_type 
                 place_cost_type 

5.2       Command-Line Options 

     VPR has a lot of options. The options most people will be interested in are -inner_num, - 
route_chan_width, and -route_type. In general for the other options the defaults are fine, and 
only people looking at how different CAD algorithms perform will try many of them. To 
understand what the more esoteric placer and router options actually do, buy [3] or download 
[7, 8, 9, 10] from the author’s web page (http://www.eecg.toronto.edu/~vaughn). 
     In the following text, values in angle brackets, e.g. <int>, should be replaced by the 
appropriate filename or number. Values in curly braces separated by vertical bars, e.g. {on | 
off}, indicate all the permissible choices for an option. 

5.2.1 General Options 

     -nodisp 
          Disables all graphics. Useful if you're not running X Windows. 
          Default: graphics enabled. 

     -auto <int> 
          Can be 0, 1, or 2. This sets how often you must click Proceed to continue execution after 
          viewing the graphics. The higher the number, the more infrequently the program will pause. 
          Default: 1. 

     -route_only 
          Take an existing placement from the placement file specified on the command line and route it. 
          Default: off. 

     -place_only 
          Place the circuit, but do not route it. 
          Default: off. 

     -timing_analysis { on | off } 
          Turn timing analysis of the routing on or off. If it is off, you don’t have to specify the various 
          timing analysis parameters in the architecture file. 
          Default: on, unless architecture file does not have timing information 

     -timing_analyze_only_with_net_delay <float> 
          Perform timing analysis on netlist assuming all edges have the same specified delay 
          Default: off 

     -outfile_prefix <string> 
          Prefix output files with specified string. 

     -full_stats 
          Print out some extra statistics about the circuit and its routing useful for wireability analysis. 

          Default: off 


5.2.2 Placer Options 

     By default, the automatic annealing schedule [3, 9] is used. This schedule gathers statistics 
as the placement progresses, and uses them to determine how to update the temperature, 
when to exit, etc. This schedule is generally superior to any user-specified schedule. If any of 
init_t, exit_t or alpha_t is specified, the user schedule, with a fixed initial temperature, final 
temperature and temperature update factor is used. 

     -seed <int> 

     Sets the initial random seed used by the placer. 
     Default: 1. 

-num_regions <int> 
     Used only with the nonlinear cost function. VPR will compute congestion on an array of 
     num_regions X num_regions subareas. Large values of num_regions greatly slow the placer. 
     Default: 4. 

     Note: This is not supported and may not be working this release 

-enable_timing_computations {on | off} 
     Controls whether or not the placement algorithm prints estimates of the circuit speed of the 
     placement it generates. This setting affects statistics output only, not optimization behaviour. 
     Default: on if timing-driven placement is specified, off otherwise. 

-block_dist <int> 
Specifies that the placement algorithm should print out an estimate of the circuit critical path, 
assuming that each inter-block connection is between blocks a (horizontal) distance of block_dist 
logic blocks apart. This setting affects statistics output only, not optimization behaviour. 
Default: 1. (Currently the code that prints out this lower bound is #ifdef ’ed out in place.c -- define 
PRINT_LOWER_BOUND in place.c to reactivate it.) 
-inner_num <float> 
     The number of moves attempted at each temperature is inner_num * num_blocks^(4/3) in the 
     circuit. The number of blocks in a circuit is the number of pads plus the number of clbs. 
     Changing inner_num is the best way to change the speed/quality tradeoff of the placer, as it 
     leaves the highly-efficient automatic annealing schedule on and simply changes the number of 
     moves per temperature. 
     Note: Specifying -inner_num 1 will speed up the placer by a factor of 10 while typically reducing 
     placement quality only by 10% or less (depends on the architecture). Hence users more 
     concerned with CPU time than quality may find this a more appropriate value of inner_num. 
     Default: 10. 

-init_t <float> 
     The starting temperature of the anneal for the manual annealing schedule. 
     Default: 100. 

-exit_t <float> 
     The (manual) anneal will terminate when the temperature drops below the exit temperature. 
     Default: 0.01. 

-alpha_t <float> 
     The temperature is updated by multiplying the old temperature by alpha_t when the manual 
     annealing schedule is enabled. 
     Default: 0.8. 

-fix_pins {random | <file.pads>} 
     Do not allow the placer to move the I/O locations about during the anneal. Instead, lock each 
     I/O pad to some location at the start of the anneal. 

     If -fix_pins random is specified, each I/O block is locked to a random pad location to model 
     the effect of poor board-level I/O constraints. If any word other than random is specified after - 
     fix_pins, that string is taken to be the name of a file listing the desired location of each I/O block 
     in the netlist (i.e. -fix_pins <file.pads>). 
     This pad location file is in the same format as a normal placement file, but only specifies the 
     locations of I/O pads, rather than the locations of all blocks. 
     Default: off (i.e. placer chooses pad locations).