uart_top.syr

来自「RS232的UART编程」· SYR 代码 · 共 93 行

Release 8.2.03i - xst I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.83 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: uart_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "uart_top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "uart_top"
Output Format                      : NGC
Target Device                      : Automotive CoolRunner2

---- Source Options
Top Module Name                    : uart_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : uart_top.lso
verilog2001                        : YES
safe_implementation                : No
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "uart_top.v" in library work
Module <uart_top> compiled
No errors in compilation
Analysis of file <"uart_top.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
ERROR:HDLCompilers:87 - "uart_top.v" line 38 Could not find module/primitive 'baud_gen'
ERROR:HDLCompilers:87 - "uart_top.v" line 74 Could not find module/primitive 'uart_tx'
ERROR:HDLCompilers:87 - "uart_top.v" line 83 Could not find module/primitive 'uart_rx'
ERROR:Xst - Unexpected error found while building hierarchy.
--> 

Total memory usage is 110656 kilobytes

Number of errors   :    4 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)