shiftreg1to4.vhd

红外4PPM解码的源程序

library ieee;
use ieee.std_logic_1164.all;
entity shiftreg1to4 is
port(clk,d:in std_logic;
     q:out std_logic_vector(3 downto 0));
end shiftreg1to4;
architecture behavior of shiftreg1to4 is
begin
process(clk)
variable count:integer range 0 to 7;
variable temp:std_logic_vector(3 downto 0);
begin
if(clk'event and clk='1') then
count:=count+1;
temp:=d & temp(3 downto 1);
if(count=4) then
q<=temp;
count:=0;
end if;
end if;
end process;
end behavior;