shiftreg1to4.rpt

红外4PPM解码的源程序

 (33)    24    B       DFFE   +  t        0      0   0    0    1    1    1  temp2 (:12)
 (34)    23    B       DFFE   +  t        0      0   0    0    1    1    0  temp1 (:13)
 (36)    22    B       TFFE   +  t        0      0   0    0    3    4    1  count2 (:15)
 (37)    21    B       TFFE   +  t        0      0   0    0    1    4    1  count1 (:16)
 (31)    26    B       TFFE   +  t        0      0   0    0    0    4    2  count0 (:17)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:              d:\mux puls file\jm\shiftreg1to4.rpt
shiftreg1to4

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                             Logic cells placed in LAB 'B'
        +------------------- LC17 q0
        | +----------------- LC18 q1
        | | +--------------- LC19 q2
        | | | +------------- LC20 q3
        | | | | +----------- LC25 temp3
        | | | | | +--------- LC24 temp2
        | | | | | | +------- LC23 temp1
        | | | | | | | +----- LC22 count2
        | | | | | | | | +--- LC21 count1
        | | | | | | | | | +- LC26 count0
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> * - - - - - - - - - | - * | <-- q0
LC18 -> - * - - - - - - - - | - * | <-- q1
LC19 -> - - * - - - - - - - | - * | <-- q2
LC20 -> - - - * - - - - - - | - * | <-- q3
LC25 -> - - * - - * - - - - | - * | <-- temp3
LC24 -> - * - - - - * - - - | - * | <-- temp2
LC23 -> * - - - - - - - - - | - * | <-- temp1
LC22 -> * * * * - - - * - - | - * | <-- count2
LC21 -> * * * * - - - * * - | - * | <-- count1
LC26 -> * * * * - - - * * * | - * | <-- count0

Pin
43   -> - - - - - - - - - - | - - | <-- clk
4    -> - - - * * - - - - - | - * | <-- d


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:              d:\mux puls file\jm\shiftreg1to4.rpt
shiftreg1to4

** EQUATIONS **

clk      : INPUT;
d        : INPUT;

-- Node name is ':17' = 'count0' 
-- Equation name is 'count0', location is LC026, type is buried.
count0   = TFFE( VCC, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':16' = 'count1' 
-- Equation name is 'count1', location is LC021, type is buried.
count1   = TFFE( count0, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':15' = 'count2' 
-- Equation name is 'count2', location is LC022, type is buried.
count2   = TFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 =  count0 &  count1 &  count2;

-- Node name is 'q0' = ':9' 
-- Equation name is 'q0', type is output 
 q0      = TFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 =  count0 &  count1 & !count2 & !q0 &  temp1
         #  count0 &  count1 & !count2 &  q0 & !temp1;

-- Node name is 'q1' = ':7' 
-- Equation name is 'q1', type is output 
 q1      = TFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  count0 &  count1 & !count2 & !q1 &  temp2
         #  count0 &  count1 & !count2 &  q1 & !temp2;

-- Node name is 'q2' = ':5' 
-- Equation name is 'q2', type is output 
 q2      = TFFE( _EQ004, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  count0 &  count1 & !count2 & !q2 &  temp3
         #  count0 &  count1 & !count2 &  q2 & !temp3;

-- Node name is 'q3' = ':3' 
-- Equation name is 'q3', type is output 
 q3      = TFFE( _EQ005, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  count0 &  count1 & !count2 &  d & !q3
         #  count0 &  count1 & !count2 & !d &  q3;

-- Node name is ':13' = 'temp1' 
-- Equation name is 'temp1', location is LC023, type is buried.
temp1    = DFFE( temp2 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':12' = 'temp2' 
-- Equation name is 'temp2', location is LC024, type is buried.
temp2    = DFFE( temp3 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);

-- Node name is ':11' = 'temp3' 
-- Equation name is 'temp3', location is LC025, type is buried.
temp3    = DFFE( d $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                       d:\mux puls file\jm\shiftreg1to4.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,331K