📄 jm.rpt
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Device-Specific Information: d:\mux puls file\jm\jm.rpt
jm
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC17 dataout
| +----------------------------- LC29 |DECODER4TO2:1|~87~1
| | +--------------------------- LC30 |DECODER4TO2:1|~102~1
| | | +------------------------- LC18 |FENPINQI4:4|LPM_ADD_SUB:80|addcore:adder|addcore:adder0|ps1
| | | | +----------------------- LC19 |FENPINQI4:4|:2
| | | | | +--------------------- LC20 |FENPINQI4:4|counter
| | | | | | +------------------- LC24 |FENPINQI4:4|counter13
| | | | | | | +----------------- LC31 |FENPINQI4:4|counter12
| | | | | | | | +--------------- LC21 |SHIFTREG1TO4:2|:3
| | | | | | | | | +------------- LC22 |SHIFTREG1TO4:2|:5
| | | | | | | | | | +----------- LC23 |SHIFTREG1TO4:2|:7
| | | | | | | | | | | +--------- LC25 |SHIFTREG1TO4:2|:9
| | | | | | | | | | | | +------- LC28 |SHIFTREG1TO4:2|count2
| | | | | | | | | | | | | +----- LC27 |SHIFTREG2TO1:3|count1
| | | | | | | | | | | | | | +--- LC26 |SHIFTREG2TO1:3|count0
| | | | | | | | | | | | | | | +- LC32 |SHIFTREG2TO1:3|reg20
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> * - - - - - - - - - - - - - - - | - * | <-- dataout
LC29 -> - * - - - - - - - - - - - - - * | - * | <-- |DECODER4TO2:1|~87~1
LC30 -> * - * - - - - - - - - - - - - - | - * | <-- |DECODER4TO2:1|~102~1
LC18 -> - - - - - - * * - - - - - - - - | * * | <-- |FENPINQI4:4|LPM_ADD_SUB:80|addcore:adder|addcore:adder0|ps1
LC19 -> * - - - * - - - - - - - - * * * | - * | <-- |FENPINQI4:4|:2
LC20 -> - - - - * * - - - - - - - - - - | - * | <-- |FENPINQI4:4|counter
LC24 -> - - - * * * * - - - - - - - - - | - * | <-- |FENPINQI4:4|counter13
LC31 -> - - - * * * * * - - - - - - - - | - * | <-- |FENPINQI4:4|counter12
LC21 -> - * * - - - - - * - - - - - - - | - * | <-- |SHIFTREG1TO4:2|:3
LC22 -> - * * - - - - - - * - - - - - - | - * | <-- |SHIFTREG1TO4:2|:5
LC23 -> - * * - - - - - - - * - - - - - | - * | <-- |SHIFTREG1TO4:2|:7
LC25 -> - * * - - - - - - - - * - - - - | - * | <-- |SHIFTREG1TO4:2|:9
LC28 -> - - - - - - - - * * * * * - - - | - * | <-- |SHIFTREG1TO4:2|count2
LC27 -> * - - - - - - - - - - - - * * * | - * | <-- |SHIFTREG2TO1:3|count1
LC26 -> * - - - - - - - - - - - - * * * | - * | <-- |SHIFTREG2TO1:3|count0
LC32 -> * - - - - - - - - - - - - - - * | - * | <-- |SHIFTREG2TO1:3|reg20
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
1 -> - - - - - - - - - - - - - - - - | - - | <-- cr
4 -> - - - - - - - - * - - - - - - - | * * | <-- datain
LC4 -> - - - - - - - - * * * * * - - - | * * | <-- |FENPINQI2:5|:2
LC12 -> - - - * * * - - - - - - - - - - | - * | <-- |FENPINQI4:4|counter11
LC3 -> - - - * * * * * - - - - - - - - | * * | <-- |FENPINQI4:4|counter10
LC1 -> - - - - - - - - - * - - - - - - | * * | <-- |SHIFTREG1TO4:2|temp3
LC2 -> - - - - - - - - - - * - - - - - | * * | <-- |SHIFTREG1TO4:2|temp2
LC8 -> - - - - - - - - - - - * - - - - | - * | <-- |SHIFTREG1TO4:2|temp1
LC6 -> - - - - - - - - * * * * * - - - | - * | <-- |SHIFTREG1TO4:2|count1
LC5 -> - - - - - - - - * * * * * - - - | * * | <-- |SHIFTREG1TO4:2|count0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\mux puls file\jm\jm.rpt
jm
** EQUATIONS **
clk : INPUT;
cr : INPUT;
datain : INPUT;
-- Node name is 'dataout' = '|SHIFTREG2TO1:3|reg21'
-- Equation name is 'dataout', type is output
dataout = DFFE( _EQ001 $ GND, _LC019, GLOBAL( cr), VCC, VCC);
_EQ001 = dataout & !_LC026 & !_LC027 & _X001
# !_LC026 & !_LC027 & _LC030
# _LC032 & _X001;
_X001 = EXP(!_LC026 & !_LC027);
-- Node name is '|DECODER4TO2:1|~87~1'
-- Equation name is '_LC029', type is buried
-- synthesized logic cell
_LC029 = LCELL( _EQ002 $ VCC);
_EQ002 = !_LC021 & _LC022 & !_LC023 & !_LC025
# _LC021 & !_LC022 & !_LC023 & !_LC025
# _LC023 & _LC025 & !_LC029
# !_LC023 & !_LC025 & !_LC029
# !_LC029 & _X002;
_X002 = EXP(!_LC021 & !_LC022);
-- Node name is '|DECODER4TO2:1|~102~1'
-- Equation name is '_LC030', type is buried
-- synthesized logic cell
_LC030 = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC021 & !_LC022 & _LC023 & !_LC025
# _LC021 & !_LC022 & !_LC023 & !_LC025
# _LC022 & _LC025 & !_LC030
# !_LC022 & !_LC025 & !_LC030
# !_LC030 & _X003;
_X003 = EXP(!_LC021 & !_LC023);
-- Node name is '|FENPINQI2:5|:4' = '|FENPINQI2:5|counter'
-- Equation name is '_LC013', type is buried
_LC013 = TFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC007 & !_LC014 & !_LC015 & !_LC016;
-- Node name is '|FENPINQI2:5|:8' = '|FENPINQI2:5|counter10'
-- Equation name is '_LC007', type is buried
_LC007 = TFFE(!_EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC007 & !_LC014 & !_LC015 & !_LC016;
-- Node name is '|FENPINQI2:5|:7' = '|FENPINQI2:5|counter11'
-- Equation name is '_LC016', type is buried
_LC016 = TFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC007 & _LC014
# _LC007 & _LC015
# _LC007 & _LC016;
-- Node name is '|FENPINQI2:5|:6' = '|FENPINQI2:5|counter12'
-- Equation name is '_LC015', type is buried
_LC015 = TFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC007 & _LC016;
-- Node name is '|FENPINQI2:5|:5' = '|FENPINQI2:5|counter13'
-- Equation name is '_LC014', type is buried
_LC014 = TFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC007 & _LC015 & _LC016;
-- Node name is '|FENPINQI2:5|:2'
-- Equation name is '_LC004', type is buried
_LC004 = TFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !_LC004 & _LC007 & _LC013 & !_LC014 & !_LC015 & !_LC016
# _LC004 & _LC007 & !_LC013 & !_LC014 & !_LC015 & !_LC016;
-- Node name is '|FENPINQI4:4|:4' = '|FENPINQI4:4|counter'
-- Equation name is '_LC020', type is buried
_LC020 = TFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !_LC003 & _LC012 & !_LC024 & !_LC031;
-- Node name is '|FENPINQI4:4|:8' = '|FENPINQI4:4|counter10'
-- Equation name is '_LC003', type is buried
_LC003 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|FENPINQI4:4|:7' = '|FENPINQI4:4|counter11'
-- Equation name is '_LC012', type is buried
_LC012 = DFFE(!_LC018 $ _LC003, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|FENPINQI4:4|:6' = '|FENPINQI4:4|counter12'
-- Equation name is '_LC031', type is buried
_LC031 = DFFE( _EQ011 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = _LC003 & !_LC018 & !_LC031
# _LC018 & _LC031
# !_LC003 & _LC031;
-- Node name is '|FENPINQI4:4|:5' = '|FENPINQI4:4|counter13'
-- Equation name is '_LC024', type is buried
_LC024 = TFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC003 & !_LC018 & _LC031;
-- Node name is '|FENPINQI4:4|LPM_ADD_SUB:80|addcore:adder|addcore:adder0|ps1' from file "addcore.tdf" line 150, column 7
-- Equation name is '_LC018', type is buried
_LC018 = LCELL( _EQ013 $ !_LC012);
_EQ013 = !_LC003 & _LC012 & !_LC024 & !_LC031;
-- Node name is '|FENPINQI4:4|:2'
-- Equation name is '_LC019', type is buried
_LC019 = TFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !_LC003 & _LC012 & !_LC019 & _LC020 & !_LC024 & !_LC031
# !_LC003 & _LC012 & _LC019 & !_LC020 & !_LC024 & !_LC031;
-- Node name is '|SHIFTREG1TO4:2|:17' = '|SHIFTREG1TO4:2|count0'
-- Equation name is '_LC005', type is buried
_LC005 = TFFE( VCC, _LC004, VCC, VCC, VCC);
-- Node name is '|SHIFTREG1TO4:2|:16' = '|SHIFTREG1TO4:2|count1'
-- Equation name is '_LC006', type is buried
_LC006 = TFFE( _LC005, _LC004, VCC, VCC, VCC);
-- Node name is '|SHIFTREG1TO4:2|:15' = '|SHIFTREG1TO4:2|count2'
-- Equation name is '_LC028', type is buried
_LC028 = TFFE( _EQ015, _LC004, VCC, VCC, VCC);
_EQ015 = _LC005 & _LC006 & _LC028;
-- Node name is '|SHIFTREG1TO4:2|:13' = '|SHIFTREG1TO4:2|temp1'
-- Equation name is '_LC008', type is buried
_LC008 = DFFE( _LC002 $ GND, _LC004, VCC, VCC, VCC);
-- Node name is '|SHIFTREG1TO4:2|:12' = '|SHIFTREG1TO4:2|temp2'
-- Equation name is '_LC002', type is buried
_LC002 = DFFE( _LC001 $ GND, _LC004, VCC, VCC, VCC);
-- Node name is '|SHIFTREG1TO4:2|:11' = '|SHIFTREG1TO4:2|temp3'
-- Equation name is '_LC001', type is buried
_LC001 = DFFE( datain $ GND, _LC004, VCC, VCC, VCC);
-- Node name is '|SHIFTREG1TO4:2|:3'
-- Equation name is '_LC021', type is buried
_LC021 = TFFE( _EQ016, _LC004, VCC, VCC, VCC);
_EQ016 = datain & _LC005 & _LC006 & !_LC021 & !_LC028
# !datain & _LC005 & _LC006 & _LC021 & !_LC028;
-- Node name is '|SHIFTREG1TO4:2|:5'
-- Equation name is '_LC022', type is buried
_LC022 = TFFE( _EQ017, _LC004, VCC, VCC, VCC);
_EQ017 = _LC001 & _LC005 & _LC006 & !_LC022 & !_LC028
# !_LC001 & _LC005 & _LC006 & _LC022 & !_LC028;
-- Node name is '|SHIFTREG1TO4:2|:7'
-- Equation name is '_LC023', type is buried
_LC023 = TFFE( _EQ018, _LC004, VCC, VCC, VCC);
_EQ018 = _LC002 & _LC005 & _LC006 & !_LC023 & !_LC028
# !_LC002 & _LC005 & _LC006 & _LC023 & !_LC028;
-- Node name is '|SHIFTREG1TO4:2|:9'
-- Equation name is '_LC025', type is buried
_LC025 = TFFE( _EQ019, _LC004, VCC, VCC, VCC);
_EQ019 = _LC005 & _LC006 & _LC008 & !_LC025 & !_LC028
# _LC005 & _LC006 & !_LC008 & _LC025 & !_LC028;
-- Node name is '|SHIFTREG2TO1:3|:7' = '|SHIFTREG2TO1:3|count0'
-- Equation name is '_LC026', type is buried
_LC026 = DFFE( _EQ020 $ GND, _LC019, VCC, VCC, VCC);
_EQ020 = !_LC026 & !_LC027;
-- Node name is '|SHIFTREG2TO1:3|:6' = '|SHIFTREG2TO1:3|count1'
-- Equation name is '_LC027', type is buried
_LC027 = TFFE(!_EQ021, _LC019, VCC, VCC, VCC);
_EQ021 = !_LC026 & !_LC027;
-- Node name is '|SHIFTREG2TO1:3|:8' = '|SHIFTREG2TO1:3|reg20'
-- Equation name is '_LC032', type is buried
_LC032 = DFFE( _EQ022 $ GND, _LC019, GLOBAL( cr), VCC, VCC);
_EQ022 = !_LC026 & !_LC027 & _LC029
# _LC032 & _X001;
_X001 = EXP(!_LC026 & !_LC027);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\mux puls file\jm\jm.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,770K
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