hardinit.msa

ATJ2091N 54版源程序

/*
********************************************************************************
*                       ACTOS
*                  UI Init function
*
*                (c) Copyright 2003-2004, Actions Co,Ld.
*                        All Right Reserved
*
* File   : UI_HardInit.msa
* By     : vicky
* Version: 1> v1.00     first version     11/26/2003 15:21PM
********************************************************************************
*/
#include "UI_S0724.h"  

#define    InitClear    Displaylength+4


    module  UI_HardInit
    
    public  sUI_HardInit
    extern  sUI_CmdTrans
    //extern  UI_Entrance
    extern  REG02_Buff
    extern  REG2f_Buff
    extern  REGee_Buff
    
    rseg    BBD_IE
    rseg    BBC_IE 
         
sUI_HardInit:
    push    bc
    push    de
//******************************** Port configuration***************************
    in      a,(RST_GIO_EN_REG)       
    or      RST_SET_BIT         
    out     (RST_GIO_EN_REG),a
            
    in      a,(A0_GIO_EN_REG)        
    or      A0_SET_BIT           
    out     (A0_GIO_EN_REG),a
    
//******************************** Enable CE# and  clear CS1B******************
    in      a,(REG02_EMHiPageReg)    //REG02 bak
    ld      (REG02_Buff),a
    in      a,(REG02_EMHiPageReg)
    or      CE_EN_BIT
    out     (REG02_EMHiPageReg),a         
         
//******************************** Reset pin high ******************************
    ld      c,RST_SET_BIT        
    ld      d,RST_CLR_BIT
    in      a,(RST_GIO_DATA_REG)
    or      c
    out     (RST_GIO_DATA_REG),a    //RESET pin high
    out     (RST_GIO_DATA_REG),a    //Delay
    out     (RST_GIO_DATA_REG),a    //Delay
    and     d
    out     (RST_GIO_DATA_REG),a    //RESET pin low
    out     (RST_GIO_DATA_REG),a    //Delay
    out     (RST_GIO_DATA_REG),a    //Delay
    out     (RST_GIO_DATA_REG),a    //Delay
    out     (RST_GIO_DATA_REG),a    //Delay
    or      c
    out     (RST_GIO_DATA_REG),a    //RESET pin high
    out     (RST_GIO_DATA_REG),a    //Delay
    out     (RST_GIO_DATA_REG),a    //Delay
/*    
//******************************** Value to display interrupt vector ***********
    ld      a,0xc3
    ld      (RSTDisplayAPI),a
    ld      hl,UI_Entrance
    ld      (RSTDisplayAPI+1),hl
    
//******************************** Initial configure ***************************
*/    
    ld      c,0xa2        //bias select    1/6
    call    sUI_CmdTrans
    ld      c,0xa1        //ADC select(s131->s0)
    call    sUI_CmdTrans
    ld      c,0xc0        //SHL select(com0-com31)        
    call    sUI_CmdTrans
    
    ld      c,0x27        //1+Rb/Ra=3.5(0x20:3.0,0x21:3.5,0x22:4,...,0x27:6.5)
    call    sUI_CmdTrans
    ld      c,0x81        //Electronic volume model set
    call    sUI_CmdTrans
    ld      c,0x0c        //v0=(1+Rb/Ra)*(1-a/162),a=51(0x00:a=63,...,0x3f:a=0),v0=5.03v
    call    sUI_CmdTrans
    ld      c,0x2f        //Power control setting
    call    sUI_CmdTrans
       
    ld      c,0xaf        //Display on
    call    sUI_CmdTrans
    ld      c,0xa4        //Display all points off
    call    sUI_CmdTrans
    
//******************************** First clear screen **************************
    ld      c,0xb0        //Page address set:page 0
    call    sUI_CmdTrans    
    ld      c,0x10        //Column address set upper bit:0        
    call    sUI_CmdTrans
    ld      c,0x00        //Column address set lower bit:0
    call    sUI_CmdTrans 
    
    ld      b,InitClear
    in      a,(A0_GIO_DATA_REG)    
    or      A0_SET_BIT
    out     (A0_GIO_DATA_REG),a    //A0=1;Data bits:data
    xor     a

Clearline0_Cycle:
    ld      (0x8001),a
    djnz    Clearline0_Cycle
    
    ld      c,0xb1        //Page address set:page 1
    call    sUI_CmdTrans
    ld      c,0x10
    call    sUI_CmdTrans
    ld      c,0x0
    call    sUI_CmdTrans 
    ld      b,InitClear

    ld      b,InitClear
    in      a,(A0_GIO_DATA_REG)    
    or      A0_SET_BIT
    out     (A0_GIO_DATA_REG),a    //A0=1;Data bits:data
    xor     a
    
Clearline1_Cycle:
    ld      (0x8001),a
    djnz    Clearline1_Cycle
    
    ld      c,0xb2        //Page address set:page 2
    call    sUI_CmdTrans
    ld      c,0x10
    call    sUI_CmdTrans
    ld      c,0x00
    call    sUI_CmdTrans 
    
    ld      b,InitClear
    in      a,(A0_GIO_DATA_REG)    //A0=1;Data bits:data 
    or      A0_SET_BIT
    out     (A0_GIO_DATA_REG),a
    xor     a
    
Clearline2_Cycle:
    ld      (0x8001),a
    djnz    Clearline2_Cycle
    
    ld      c,0xb3        //Page address set:page 3
    call    sUI_CmdTrans
    ld      c,0x10
    call    sUI_CmdTrans
    ld      c,0x0
    call    sUI_CmdTrans 
    ld      b,InitClear

    in      a,(A0_GIO_DATA_REG)    //A0=1;Data bits:data 
    or      A0_SET_BIT
    out     (A0_GIO_DATA_REG),a
    xor     a
    
Clearline3_Cycle:
    ld      (0x8001),a
    djnz    Clearline3_Cycle
    
    ld      a,(REG02_Buff)
    out     (REG02_EMHiPageReg),a          
    
    pop     de
    pop     bc
    ret  
        
/*
********************************************************************************
*  the end of file
********************************************************************************
*/
        end