armiu_drstg.vhd

arm vhdl rtl code,can synthesis

      when type_arm_ldc =>
        t.cmdcli.ctrli := t.ctrli;
        t.cmdcli.fromCP_busy := i.fromCPDE_busy;
        t.cmdcli.fromCP_last := i.fromCPDE_last;
        t.ctrlo := cmdclo.ctrlo;
        
      when type_arm_mrc |
           type_arm_mcr =>

        t.cmdcri.fromCP_busy := i.fromCPDE_busy;
        t.cmdcri.ctrli := t.ctrli;
        t.ctrlo := cmdcro.ctrlo;
        t.r1_src := cmdcro.r1_src;
        t.rd_src := cmdcro.rd_src;
        
        t.pctrl.ex.exop_data_src := apc_datasrc_none;  -- keep pctrl.data1
        
      when type_arm_swi =>
        t.trap.trap := '1';
        t.trap.traptype := apm_trap_swi;
        
      when type_arm_undefined =>
        t.trap.trap := '1';
        t.trap.traptype := apm_trap_undef;
        
      when type_arm_cdp =>
      when others => 
    end case;
    
    if i.fromDE_insn_r.trap = '1' then
      t.trap.trap := '1';
      t.trap.traptype := apm_trap_prefch;
    end if;
    
    -- traps
    if t.trap.trap = '1' then

      t.m1_valid := '0';
      t.m2_valid := '0';

      -- [frame:] r14 calculation 
      --
      --            RRSTG       RSSTG       EXSTG       DMSTG       MESTG       WRSTG
      --       --+-----------+-----------+-----------+-----------+-----------+----------+
      -- <pc+8>->+-----------+----------op1          |           |           |
      --         |           |           | \         |           |           |
      --         |  (regread)| (noshift) | +(aluop)  |  (trans)  | (dcache)  | +->(write)
      --         |           |           | /   |     |           |           | |
      --         |           |  <offset>op2    |     |           |           | |
      --       --+-----------+-----------+-----+-----+-----------+-----------+-+--------+
      --                                       |                               |
      --         pctrl.data1 (as r14-data) :   +-------------------------------+

      t.pctrl := t.pctrl_bypass;
      t.r1_src := acm_none;
      t.r2_src := acm_none;
      t.rd_src := acm_rdnone;
      
      t.pctrl.rs.rsop_op1_src := apc_opsrc_none;
      t.pctrl.rs.rsop_op2_src := apc_opsrc_none;
      t.pctrl.ex.exop_data_src := apc_datasrc_aluout;
      t.pctrl.data1 := i.fromDE_insn_r.insn.pc_8;
      t.pctrl.data2 := (others => '0');
      
      case t.trap.traptype is
        when apm_trap_reset    =>
          
-- $(del)
-- R14_svc = UNPREDICTABLE value
-- SPSR_svc = UNPREDICTABLE value
-- CPSR[4:0] = 0b10011 /* Enter Supervisor mode */
-- CPSR[5] = 0 /* Execute in ARM state */
-- CPSR[6] = 1 /* Disable fast interrupts */
-- CPSR[7] = 1 /* Disable normal interrupts */
-- if high vectors configured then
-- PC = 0xFFFF0000
-- else
-- PC = 0x00000000
-- $(/del)
          
        when apm_trap_undef =>

-- $(del)
-- R14_und = address of next instruction after the undefined instruction
-- SPSR_und = CPSR
-- CPSR[4:0] = 0b11011 /* Enter Undefined mode */
-- CPSR[5] = 0 /* Execute in ARM state */
-- /* CPSR[6] is unchanged */
-- CPSR[7] = 1 /* Disable normal interrupts */
-- if high vectors configured then
-- PC = 0xFFFF0004
-- else
-- PC = 0x00000004
-- $(/del)
          
          t.pctrl.data2 := LIN_MINFOUR;
          
        when apm_trap_swi      =>

-- $(del)
-- R14_svc = address of next instruction after the SWI instruction
-- SPSR_svc = CPSR
-- CPSR[4:0] = 0b10011 /* Enter Supervisor mode */
-- CPSR[5] = 0 /* Execute in ARM state */
-- /* CPSR[6] is unchanged */
-- CPSR[7] = 1 /* Disable normal interrupts */
-- if high vectors configured then
-- PC = 0xFFFF0008
-- else
-- PC = 0x00000008
-- $(/del)
          
          t.pctrl.data2 := LIN_MINFOUR;
          
        when apm_trap_prefch =>

-- $(del)
-- R14_abt = address of the aborted instruction + 4
-- SPSR_abt = CPSR
-- CPSR[4:0] = 0b10111 /* Enter Abort mode */
-- CPSR[5] = 0 /* Execute in ARM state */
-- /* CPSR[6] is unchanged */
-- CPSR[7] = 1 /* Disable normal interrupts */
-- if high vectors configured then
-- PC = 0xFFFF000C
-- else
-- PC = 0x0000000C
-- $(/del)
          
          t.pctrl.data2 := LIN_MINFOUR;
          
        when apm_trap_dabort   =>

-- $(del)
-- R14_abt = address of the aborted instruction + 8
-- SPSR_abt = CPSR
-- CPSR[4:0] = 0b10111 /* Enter Abort mode */
-- CPSR[5] = 0 /* Execute in ARM state */
-- /* CPSR[6] is unchanged */
-- CPSR[7] = 1 /* Disable normal interrupts */
-- if high vectors configured then
-- PC = 0xFFFF0010
-- else
-- PC = 0x00000010
-- $(/del)
          -- will not happen (later in pipeline)
          -- pragma translate_off
          assert false report "Wrong initialization of trap type" severity failure;
          -- pragma translate_on
          
        when apm_trap_irq      =>

-- $(del)
-- R14_irq = address of next instruction to be executed + 4
-- SPSR_irq = CPSR
-- CPSR[4:0] = 0b10010 /* Enter IRQ mode */
-- CPSR[5] = 0 /* Execute in ARM state */
-- /* CPSR[6] is unchanged */
-- CPSR[7] = 1 /* Disable normal interrupts */
-- if high vectors configured then
-- PC = 0xFFFF0018
-- else
-- PC = 0x00000018
-- $(/del)

          --v.pctrl.MESTGxWRSTG_data := t.regshiefto.RSSTG_pc_4;
          
        when apm_trap_fiq      =>

-- $(del)
-- R14_fiq = address of next instruction to be executed + 4
-- SPSR_fiq = CPSR
-- CPSR[4:0] = 0b10001 /* Enter FIQ mode */
-- CPSR[5] = 0 /* Execute in ARM state */
-- CPSR[6] = 1 /* Disable fast interrupts */
-- CPSR[7] = 1 /* Disable normal interrupts */
-- if high vectors configured then
-- PC = 0xFFFF001C
-- else
-- PC = 0x0000001C
-- $(/del)

          --v.pctrl.MESTGxWRSTG_data := t.regshiefto.RSSTG_pc_4;
          
        when others            => 
      end case;

    end if;
    t.pctrl.wr.wrop_trap := t.trap;
    
    -- src registers
    t.m1_valid  := '1';
    case t.r1_src is
      when acm_rrn  => t.m1 := t.rn; 
      when acm_rrm  => t.m1 := t.rm; 
      when acm_rrs  => t.m1 := t.rs; 
      when acm_rrd  => t.m1 := t.rd; 
      when acm_none => t.m1_valid := '0';
      when acm_local => t.m1_valid := '1';
      when others => null;
    end case;
    t.rr1 := apm_bankreg(t.rmode,t.m1);
    
    t.m2_valid  := '1';
    case t.r2_src is
      when acm_rrn  => t.m2 := t.rn; 
      when acm_rrm  => t.m2 := t.rm; 
      when acm_rrs  => t.m2 := t.rs; 
      when acm_rrd  => t.m2 := t.rd; 
      when acm_none => t.m2_valid := '0';
      when acm_local => t.m2_valid := '1';
      when others => 
    end case;
    t.rr2 := apm_bankreg(t.rmode,t.m2);

    t.pctrl.wr.wrop_rdvalid := '1';
    case t.rd_src is
      when acm_rdrrn  => t.md := t.rn; 
      when acm_rdrrd  => t.md := t.rd; 
      when acm_rdpc   => t.md := APM_REG_PC; 
      when acm_rdlink => t.md := APM_REG_LINK; 
      when acm_rdnone => t.pctrl.wr.wrop_rdvalid := '0'; 
      when acm_rdlocal => t.pctrl.wr.wrop_rdvalid := '1'; 
      when others => 
    end case;
    t.pctrl.wr.wrop_rd := apm_bankreg(t.rmode,t.md);
    
    t.micro.pctrl := t.pctrl;
    t.micro.r1 := t.rr1;
    t.micro.r2 := t.rr2;
    t.micro.r1_valid := t.m1_valid;
    t.micro.r2_valid := t.m2_valid;
    t.micro.pctrl.valid := '0';
    t.micro.valid := '1';
    
    -- microcode counter
    t.nextmicro := i.fromRR_nextmicro_v;
    
    if t.ctrlo.hold = '1' then
      t.nextmicro := '0';
      t.micro.valid := '0';
    end if;
        
    -- invalid insn & pipeline flush
    if (i.fromDE_insn_r.insn.valid = '0') or
       (not (t.commit = '1')) then
      t.ctrlo.nextinsn := '1';
      t.nextmicro := '1';
      t.micro.valid := '0';
    end if;
    t.o.toRR_micro_v := t.micro;
    
    if i.pstate.hold_r.hold = '0' then
      if t.nextmicro = '1' then
        if t.ctrlo.nextinsn = '1' then
          v.cnt := (others => '0');
          v.reglist := i.fromDE_insn_v.insn.insn(ADE_REGLIST_U downto ADE_REGLIST_D);
        else
          if t.ctrlo.nextcnt = '1' then
            lin_incdec(r.cnt,v.cnt,'1','1');
            if t.nr_c = '1' then
              v.reglist(t.nr_i) := '0';
            end if;
          end if;
        end if;
      else
        t.ctrlo.nextinsn := '0';
      end if;
    end if;
    
    
    t.o.nextinsn_v := t.ctrlo.nextinsn;
    t.o.id := i.fromDE_insn_r.insn.id;

    -- reset
    if ( rst = '0' ) then
    end if;
    
    c <= v;

    cmdali <= t.cmdali;
    cmdsri <= t.cmdsri;
    cmdldi <= t.cmdldi;
    cmdsti <= t.cmdsti;
    cmdlmi <= t.cmdlmi;
    cmdsmi <= t.cmdsmi;
    cmdswi <= t.cmdswi;
    cmdcri <= t.cmdcri;
    cmdcli <= t.cmdcli;
    cmdcsi <= t.cmdcsi;
    cmdbli <= t.cmdbli;
    
    o <= t.o;
    
    -- pragma translate_off
    vdbg := rdbg;
    vdbg.dbg := t;
    vdbg.dbgpmode := adg_todbgpmode(i.pstate.fromEX_cpsr_r.wr.mode);
    vdbg.dbgrmode := adg_todbgpmode(t.rmode);
    cdbg <= vdbg;
    -- pragma translate_on  
    
  end process p0;
    
  pregs : process (clk, c)
  begin
    if rising_edge(clk) then
      r <= c;
      -- pragma translate_off
      rdbg <= cdbg;
      -- pragma translate_on
    end if;
  end process;

  al0: armcmd_al port map ( rst, clk, cmdali, cmdalo );
  sr0: armcmd_sr port map ( rst, clk, cmdsri, cmdsro );
  ld0: armcmd_ld port map ( rst, clk, cmdldi, cmdldo );
  st0: armcmd_st port map ( rst, clk, cmdsti, cmdsto );
  lm0: armcmd_lm port map ( rst, clk, cmdlmi, cmdlmo );
  sm0: armcmd_sm port map ( rst, clk, cmdsmi, cmdsmo );
  sw0: armcmd_sw port map ( rst, clk, cmdswi, cmdswo );
  cr0: armcmd_cr port map ( rst, clk, cmdcri, cmdcro );
  cl0: armcmd_cl port map ( rst, clk, cmdcli, cmdclo );
  cs0: armcmd_cs port map ( rst, clk, cmdcsi, cmdcso );
  bl0: armcmd_bl port map ( rst, clk, cmdbli, cmdblo );

end rtl;