armiu.vhd

arm vhdl rtl code,can synthesis

-- $(lic)
-- $(help_generic)
-- $(help_local)

library ieee;
use ieee.std_logic_1164.all;
use work.corelib.all;
use work.config.all;
use work.memdef.all;
use work.arm_comp.all;
use work.armpctrl.all;
use work.armcoproc.all;
use work.armcp_comp.all;
use work.cache_comp.all;

entity armiu is
  port ( 
    rst     : in  std_logic;
    clk     : in  std_logic;
    clkn    : in  std_logic;
    hold    : in cli_hold;
    ici     : out genic_type_in;
    ico     : in genic_type_out;
    dci     : out gendc_type_in;
    dco     : in gendc_type_out;
    i       : in  armiu_typ_in;
    o       : out armiu_typ_out
    );
end armiu;

architecture rtl of armiu is

  type armiu_tmp_type is record
    o       : armiu_typ_out;
    pstate  : apc_pstate;
    armiu_imstgi : armiu_imstg_typ_in;
    armiu_festgi : armiu_festg_typ_in;
    armiu_destgi : armiu_destg_typ_in;
    armiu_drstgi : armiu_drstg_typ_in;
    armiu_rrstgi : armiu_rrstg_typ_in;
    armiu_rsstgi : armiu_rsstg_typ_in;
    armiu_exstgi : armiu_exstg_typ_in;
    armiu_dmstgi : armiu_dmstg_typ_in;
    armiu_mestgi : armiu_mestg_typ_in;
    armiu_wrstgi : armiu_wrstg_typ_in;
    drid : std_logic_vector(2 downto 0);
    rrid : std_logic_vector(2 downto 0);
    rsid : std_logic_vector(2 downto 0);
    exid : std_logic_vector(2 downto 0);
    dmid : std_logic_vector(2 downto 0);
    meid : std_logic_vector(2 downto 0);
    wrid : std_logic_vector(2 downto 0);
    exclear : std_logic;
    wrclear : std_logic;
    addrvir : std_logic_vector(31 downto 0);
    branch : std_logic;
    
    ici : genic_type_in;
    dci : gendc_type_in;
    
    cpsyci  : aco_in;
  end record;
  type armiu_reg_type is record
    dummy      : std_logic;
  end record;
  type armiu_dbg_type is record
     dummy : std_logic;
     -- pragma translate_off
     dbg : armiu_tmp_type;
     -- pragma translate_on
  end record;
  signal r, c       : armiu_reg_type;
  signal rdbg, cdbg : armiu_dbg_type;

  -- iu
  signal armiu_imstgi : armiu_imstg_typ_in;
  signal armiu_imstgo : armiu_imstg_typ_out;
  signal armiu_festgi : armiu_festg_typ_in;
  signal armiu_festgo : armiu_festg_typ_out;
  signal armiu_destgi : armiu_destg_typ_in;
  signal armiu_destgo : armiu_destg_typ_out;
  signal armiu_drstgi : armiu_drstg_typ_in;
  signal armiu_drstgo : armiu_drstg_typ_out;
  signal armiu_rrstgi : armiu_rrstg_typ_in;
  signal armiu_rrstgo : armiu_rrstg_typ_out;
  signal armiu_rsstgi : armiu_rsstg_typ_in;
  signal armiu_rsstgo : armiu_rsstg_typ_out;
  signal armiu_exstgi : armiu_exstg_typ_in;
  signal armiu_exstgo : armiu_exstg_typ_out;
  signal armiu_dmstgi : armiu_dmstg_typ_in;
  signal armiu_dmstgo : armiu_dmstg_typ_out;
  signal armiu_mestgi : armiu_mestg_typ_in;
  signal armiu_mestgo : armiu_mestg_typ_out;
  signal armiu_wrstgi : armiu_wrstg_typ_in;
  signal armiu_wrstgo : armiu_wrstg_typ_out;

  -- coprocessors
  signal cpsyci  : aco_in;
  signal cpsyco  : aco_out;

begin  
    
  p0: process (clk, clkn, rst, r, hold, i, ico, dco,
               armiu_imstgo, armiu_festgo, armiu_destgo, armiu_drstgo,
               armiu_rrstgo, armiu_rsstgo, armiu_exstgo, armiu_dmstgo, 
               armiu_mestgo, armiu_wrstgo,
               cpsyco )
    variable v    : armiu_reg_type;
    variable t    : armiu_tmp_type;
    variable vdbg : armiu_dbg_type;
  begin 
    
    -- $(init(t:armiu_tmp_type))
    
    v := r;

    t.pstate.hold_r := hold;
    t.pstate.nextinsn_v := armiu_drstgo.nextinsn_v;
    t.pstate.fromEX_cpsr_r := armiu_exstgo.cpsr_r;
    
    t.pstate.fromRR_pctrl_r := armiu_rrstgo.pctrl_r;
    t.pstate.fromRS_pctrl_r := armiu_rsstgo.pctrl_r;
    t.pstate.fromEX_pctrl_r := armiu_exstgo.pctrl_r;
    t.pstate.fromDM_pctrl_r := armiu_dmstgo.pctrl_r;
    t.pstate.fromME_pctrl_r := armiu_mestgo.pctrl_r;
    t.pstate.fromWR_pctrl_r := armiu_wrstgo.pctrl_r;
    
    t.armiu_imstgi.pstate := t.pstate;
    t.armiu_festgi.pstate := t.pstate;
    t.armiu_destgi.pstate := t.pstate;
    t.armiu_drstgi.pstate := t.pstate;
    t.armiu_rrstgi.pstate := t.pstate;
    t.armiu_rsstgi.pstate := t.pstate;
    t.armiu_exstgi.pstate := t.pstate;
    t.armiu_dmstgi.pstate := t.pstate;
    t.armiu_mestgi.pstate := t.pstate;
    t.armiu_wrstgi.pstate := t.pstate;

    -- festg:
    t.armiu_festgi.ico := ico;
    t.armiu_festgi.fromIM_addrphy_v   := armiu_imstgo.toFE_addrphy_v;
    t.armiu_festgi.fromIM_addrvir_v   := armiu_imstgo.toFE_addrvir_v;
    t.armiu_festgi.fromIM_addrvalid_v := armiu_imstgo.toFE_addrvalid_v;
    t.armiu_festgi.fromIM_branch_v    := armiu_imstgo.toFE_branch_v;
    t.armiu_festgi.fromIM_trap_v      := armiu_imstgo.toFE_trap_v;
    t.ici := armiu_festgo.ici;
    
    -- destg:
    t.armiu_destgi.fromFE_insn_v := armiu_festgo.toDE_insn_v;
    t.armiu_destgi.fromFE_insn_r := armiu_festgo.toDE_insn_r;

    -- drstg:
    t.armiu_drstgi.fromDE_insn_v := armiu_destgo.toDR_insn_v;
    t.armiu_drstgi.fromDE_insn_r := armiu_destgo.toDR_insn_r;
    t.armiu_drstgi.fromRR_nextmicro_v := armiu_rrstgo.toDR_nextmicro_v;
    t.armiu_drstgi.fromWR_dabort_v := armiu_wrstgo.toDR_dabort_v;
    
    -- rrstg:
    t.armiu_rrstgi.fromDR_micro_v := armiu_drstgo.toRR_micro_v;
    t.armiu_rrstgi.fromEX_alures_v := armiu_exstgo.alures_v;
    t.armiu_rrstgi.fromWR_rd_v       := armiu_wrstgo.toRR_rd_v;
    t.armiu_rrstgi.fromWR_rd_valid_v := armiu_wrstgo.toRR_rd_valid_v;
    t.armiu_rrstgi.fromWR_rd_data_v  := armiu_wrstgo.toRR_rd_data_v;

    -- rsstg:
    t.armiu_rsstgi.fromRR_pctrl_v := armiu_rrstgo.toRS_pctrl_v;
    t.armiu_rsstgi.fromEX_alures_v := armiu_exstgo.alures_v;
    t.armiu_rsstgi.fromEX_cpsr_v := armiu_exstgo.cpsr_v;

    -- exstg:
    t.armiu_exstgi.fromRS_pctrl_v := armiu_rsstgo.toEX_pctrl_v;
    t.armiu_exstgi.fromWR_spsr_r    := armiu_wrstgo.spsr_r;
    t.armiu_exstgi.fromWR_cpsr_v    := armiu_wrstgo.toEX_cpsr_v;
    t.armiu_exstgi.fromWR_cpsrset_v := armiu_wrstgo.toEX_cpsrset_v;

    -- dmstg:
    t.armiu_dmstgi.fromEX_pctrl_v := armiu_exstgo.toDM_pctrl_v;

    -- mestg:
    t.armiu_mestgi.fromDM_pctrl_v := armiu_dmstgo.toME_pctrl_v;
    t.dci := armiu_mestgo.dci;
    t.armiu_mestgi.irqo := i.irqo;
      
    -- wrstg:
    t.armiu_wrstgi.fromME_pctrl_v := armiu_mestgo.toWR_pctrl_v;
    t.armiu_wrstgi.dco := dco;
    t.o.irqi := armiu_wrstgo.irqi;

-- clear on:
-- exstgtrap    x         x         x         x         x                                                  
-- regbra       x         x         x         x         x                                                  
-- wrbra        x         x         x         x         x         x         x         x                      
-- wrstgtrap    x         x         x         x         x         x         x         x