armdecode.vhd

arm vhdl rtl code,can synthesis

  variable arm_mov	 : std_logic;
  variable arm_mvn	 : std_logic;
  variable arm_str1	 : std_logic;
  variable arm_str2	 : std_logic;
  variable arm_str3	 : std_logic;
  variable arm_ldr1	 : std_logic;
  variable arm_undefined	 : std_logic;
  variable arm_stm	 : std_logic;
  variable arm_ldm	 : std_logic;
  variable arm_b	 : std_logic;
  variable arm_swi	 : std_logic;
  variable arm_cdp	 : std_logic;
  variable arm_mrc	 : std_logic;
  variable arm_mcr	 : std_logic;
  variable arm_stc	 : std_logic;
  variable arm_ldc	 : std_logic;
  variable vec_1	: std_logic_vector(1 downto 0);
  variable vec_2	: std_logic_vector(2 downto 0);
  variable vec_3	: std_logic_vector(4 downto 0);
  variable vec_4	: std_logic_vector(21 downto 0);
  variable vec_5	: std_logic_vector(12 downto 0);
  variable vec_6	: std_logic_vector(18 downto 0);
  variable vec_7	: std_logic_vector(4 downto 0);
  variable vec_8	: std_logic_vector(0 downto 0);
  variable vec_9	: std_logic_vector(0 downto 0);
  variable vec_10	: std_logic_vector(4 downto 0);
  variable vec_11	: std_logic_vector(0 downto 0);
  variable vec_12	: std_logic_vector(2 downto 0);
  variable vec_13	: std_logic_vector(0 downto 0);
  variable vec_14	: std_logic_vector(0 downto 0);
  variable vec_15	: std_logic_vector(0 downto 0);
  variable vec_16	: std_logic_vector(0 downto 0);
  variable vec_17	: std_logic_vector(6 downto 0);
  variable vec_18	: std_logic_vector(0 downto 0);
  variable vec_19	: std_logic_vector(0 downto 0);
  variable vec_20	: std_logic_vector(0 downto 0);
  variable vec_21	: std_logic_vector(0 downto 0);
  variable vec_22	: std_logic_vector(0 downto 0);
  variable vec_23	: std_logic_vector(0 downto 0);
  variable vec_24	: std_logic_vector(7 downto 0);
  variable vec_25	: std_logic_vector(0 downto 0);
  variable vec_26	: std_logic_vector(1 downto 0);
  variable vec_27	: std_logic_vector(0 downto 0);
  variable vec_28	: std_logic_vector(0 downto 0);
  variable vec_29	: std_logic_vector(0 downto 0);
  variable vec_30	: std_logic_vector(0 downto 0);
  variable vec_31	: std_logic_vector(0 downto 0);
  variable vec_32	: std_logic_vector(0 downto 0);
  variable vec_33	: std_logic_vector(0 downto 0);
  variable insn_return : ade_decinsn;
  variable insn : std_logic_vector(31 downto 0);
begin
  insn := insn_in;
  -- decoder assumes littleendian: word[3 2 1 0]
  insn := insn_in;
  if CFG_BO_PROC = lmd_big then
    insn := insn(7 downto 0) & insn(15 downto 8) & insn(23 downto 16) & insn(31 downto 24);
  end if;
  insn_return := type_arm_invalid;
  vec_1	 := insn(3 downto 2);
  vec_2	 := insn(31 downto 31)&insn(28 downto 28)&insn(1 downto 1);
  vec_3	 := insn(30 downto 29)&insn(15 downto 15)&insn(13 downto 13)&insn(0 downto 0);
  vec_4	 := insn(27 downto 16)&insn(14 downto 14)&insn(12 downto 4);
  arm_nop	 := '0';
  vec_5	 := insn(27 downto 24)&insn(19 downto 16)&insn(12 downto 8);
  arm_mrs	 := '0';
  vec_6	 := insn(30 downto 29)&insn(23 downto 8)&insn(0 downto 0);
  arm_bx	 := '0';
  vec_7	 := insn(30 downto 29)&insn(15 downto 15)&insn(13 downto 13)&insn(0 downto 0);
  vec_8	 := insn(14 downto 14);
  arm_mul	 := '0';
  vec_9	 := insn(14 downto 14);
  arm_mla	 := '0';
  vec_10	 := insn(19 downto 16)&insn(12 downto 12);
  arm_swp	 := '0';
  arm_sumull	 := '0';
  arm_sumlal	 := '0';
  vec_11	 := insn(12 downto 12);
  arm_strhb	 := '0';
  arm_ldrhb	 := '0';
  vec_12	 := insn(15 downto 15)&insn(13 downto 13)&insn(0 downto 0);
  vec_13	 := insn(14 downto 14);
  arm_and	 := '0';
  arm_sub	 := '0';
  vec_14	 := insn(14 downto 14);
  arm_eor	 := '0';
  arm_rsb	 := '0';
  vec_15	 := insn(14 downto 14);
  arm_add	 := '0';
  arm_sbc	 := '0';
  vec_16	 := insn(14 downto 14);
  arm_adc	 := '0';
  arm_rsc	 := '0';
  vec_17	 := insn(23 downto 20)&insn(12 downto 12)&insn(10 downto 9);
  arm_msr	 := '0';
  vec_18	 := insn(14 downto 14);
  arm_teq	 := '0';
  arm_cmn	 := '0';
  vec_19	 := insn(14 downto 14);
  arm_tst	 := '0';
  arm_cmp	 := '0';
  vec_20	 := insn(14 downto 14);
  arm_orr	 := '0';
  arm_bic	 := '0';
  vec_21	 := insn(14 downto 14);
  arm_mov	 := '0';
  arm_mvn	 := '0';
  vec_22	 := insn(12 downto 12);
  vec_23	 := insn(1 downto 1);
  arm_str1	 := '0';
  vec_24	 := insn(31 downto 28)&insn(19 downto 16);
  arm_str2	 := '0';
  vec_25	 := insn(28 downto 28);
  arm_str3	 := '0';
  arm_ldr1	 := '0';
  vec_26	 := insn(28 downto 28)&insn(1 downto 1);
  arm_undefined	 := '0';
  vec_27	 := insn(1 downto 1);
  vec_28	 := insn(12 downto 12);
  arm_stm	 := '0';
  arm_ldm	 := '0';
  arm_b	 := '0';
  vec_29	 := insn(1 downto 1);
  vec_30	 := insn(0 downto 0);
  arm_swi	 := '0';
  vec_31	 := insn(28 downto 28);
  arm_cdp	 := '0';
  vec_32	 := insn(12 downto 12);
  arm_mrc	 := '0';
  arm_mcr	 := '0';
  vec_33	 := insn(12 downto 12);
  arm_stc	 := '0';
  arm_ldc	 := '0';
case vec_1 is
  when "00" =>
    case vec_2 is
      when "000" =>
        case vec_3 is
          when "00111" =>
            case vec_4 is
              when "0000000000000000001110" =>
                arm_nop := '1';
                if arm_nop = '1' then
                insn_return := type_arm_nop;
                end if;
              when others => null;
            end case;
          when "00001" =>
            case vec_5 is
              when "0000000001111" =>
                arm_mrs := '1';
                if arm_mrs = '1' then
                insn_return := type_arm_mrs;
                end if;
              when others => null;
            end case;
          when others => null;
        end case;
      when "010" =>
        case vec_6 is
          when "0011111111001011111" =>
            arm_bx := '1';
            if arm_bx = '1' then
            insn_return := type_arm_bx;
            end if;
          when others => null;
        end case;
      when "110" =>
        case vec_7 is
          when "00000" =>
            case vec_8 is
              when "0" =>
                arm_mul := '1';
                if arm_mul = '1' then
                insn_return := type_arm_mul;
                end if;
              when others => null;
            end case;
          when "00010" =>
            case vec_9 is
              when "0" =>
                arm_mla := '1';
                if arm_mla = '1' then
                insn_return := type_arm_mla;
                end if;
              when others => null;
            end case;
          when "00001" =>
            case vec_10 is
              when "00000" =>
                arm_swp := '1';
                if arm_swp = '1' then
                insn_return := type_arm_swp;
                end if;
              when others => null;
            end case;
          when "00100" =>
            arm_sumull := '1';
            if arm_sumull = '1' then
            insn_return := type_arm_sumull;
            end if;
          when "00110" =>
            arm_sumlal := '1';
            if arm_sumlal = '1' then
            insn_return := type_arm_sumlal;
            end if;
          when others => null;
        end case;
        case vec_11 is
          when "0" =>
            arm_strhb := '1' and not (arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal);
            if arm_strhb = '1' then
            insn_return := type_arm_strhb;
            end if;
          when "1" =>
            arm_ldrhb := '1' and not (arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal);
            if arm_ldrhb = '1' then
            insn_return := type_arm_ldrhb;
            end if;
          when others => null;
        end case;
      when others => null;
    end case;
    case vec_12 is
      when "000" =>
        case vec_13 is
          when "0" =>
            arm_and := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_and = '1' then
            insn_return := type_arm_and;
            end if;
          when "1" =>
            arm_sub := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_sub = '1' then
            insn_return := type_arm_sub;
            end if;
          when others => null;
        end case;
      when "010" =>
        case vec_14 is
          when "0" =>
            arm_eor := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_eor = '1' then
            insn_return := type_arm_eor;
            end if;
          when "1" =>
            arm_rsb := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_rsb = '1' then
            insn_return := type_arm_rsb;
            end if;
          when others => null;
        end case;
      when "100" =>
        case vec_15 is
          when "0" =>
            arm_add := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_add = '1' then
            insn_return := type_arm_add;
            end if;
          when "1" =>
            arm_sbc := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_sbc = '1' then
            insn_return := type_arm_sbc;
            end if;
          when others => null;
        end case;
      when "110" =>
        case vec_16 is
          when "0" =>
            arm_adc := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_adc = '1' then
            insn_return := type_arm_adc;
            end if;
          when "1" =>
            arm_rsc := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_rsc = '1' then
            insn_return := type_arm_rsc;
            end if;
          when others => null;
        end case;
      when "011" =>
        case vec_17 is
          when "1111000" =>
            arm_msr := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_msr = '1' then
            insn_return := type_arm_msr;
            end if;
          when others => null;
        end case;
        case vec_18 is
          when "0" =>
            arm_teq := '1' and not (arm_msr or arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_teq = '1' then
            insn_return := type_arm_teq;
            end if;
          when "1" =>
            arm_cmn := '1' and not (arm_msr or arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_cmn = '1' then
            insn_return := type_arm_cmn;
            end if;
          when others => null;
        end case;
      when "001" =>
        case vec_19 is
          when "0" =>
            arm_tst := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_tst = '1' then
            insn_return := type_arm_tst;
            end if;
          when "1" =>
            arm_cmp := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_cmp = '1' then
            insn_return := type_arm_cmp;
            end if;
          when others => null;
        end case;
      when "101" =>
        case vec_20 is
          when "0" =>
            arm_orr := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_orr = '1' then
            insn_return := type_arm_orr;
            end if;
          when "1" =>
            arm_bic := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_bic = '1' then
            insn_return := type_arm_bic;
            end if;
          when others => null;
        end case;
      when "111" =>
        case vec_21 is
          when "0" =>
            arm_mov := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_mov = '1' then
            insn_return := type_arm_mov;
            end if;
          when "1" =>
            arm_mvn := '1' and not (arm_nop or arm_mrs or arm_bx or arm_mul or arm_mla or arm_swp or arm_sumull or arm_sumlal or arm_strhb or arm_ldrhb);
            if arm_mvn = '1' then
            insn_return := type_arm_mvn;
            end if;
          when others => null;
        end case;
      when others => null;
    end case;
  when "01" =>
    case vec_22 is
      when "0" =>
        case vec_23 is
          when "0" =>
            arm_str1 := '1';
            if arm_str1 = '1' then
            insn_return := type_arm_str1;
            end if;
          when "1" =>
            case vec_24 is
              when "00000000" =>
                arm_str2 := '1';
                if arm_str2 = '1' then
                insn_return := type_arm_str2;
                end if;
              when others => null;
            end case;
          when others => null;
        end case;
        case vec_25 is
          when "0" =>
            arm_str3 := '1' and not (arm_str1 or arm_str2);
            if arm_str3 = '1' then
            insn_return := type_arm_str3;
            end if;