usb_new_ep_handler_rtl.vhdl

usb rtl code, to fpga or asic

--------------------------------------------------------------------------------
--
--  P H I L I P S  C O M P A N Y  R E S T R I C T E D
--                                         
--  Copyright (c) 1998.                    
--					   
--  Philips Electronics N.V.		   
--					   
--  Philips Semiconductors		 
--  Interconnectivity and Processor Peripheral group			  
--  Bangalore, India	                   
--  All rights reserved. Reproduction in whole or in part is prohibited
--  without the written permission of the copyright owner.
--
--------------------------------------------------------------------------------
--
--  File            :  usb_new_ep_handler_rtl.vhdl 
--
--  Module          :  EP_HANDLER 
--
--  Project         :  VPB bus interface to USB 1.1 device (USBFS22)
--
--  Author          :              
--
--  Description     : The Architecture of EP handler 
--
--  Contact address : [e-mail]
--
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_CONFIGURATION.all;
use work.PCK_HANDLERS.all;

library work;
use work.PCK_APB.all;

ARCHITECTURE rtl OF ep_handler IS
 
 signal  EndTransfer_Cmd_I:   one_bit;
 signal  Read_I:              one_bit;
 signal  read_4T   :          one_bit;
 signal  DataFromUC_I:        T_UC_to_Handlers;           
 signal  DataToUC_Buffer:     byte;
 signal  count_state:         Int_TwoBits;
 signal  trans_enable_I:      one_bit; 
 signal  DataToUC_Buffer_Rdy: boolean;
 signal  ReadCmdData:         boolean; -- Read Command Data
 signal  CmdDataValid_I:      boolean;
 signal  CmdDecode:           boolean;
 signal  CmdAccept_I:         boolean;
 signal  ReadNdata:           boolean;
 signal  CmdCodeValid_Out_Q:  boolean;
 signal  if_busy_Q:           boolean;
 signal  read_req_Q:          one_bit;
 signal  read_req_2Q:         one_bit;
 signal  Rx_N_Data_i:         integer range 0 to MAX_OVERFLOW_SIZE;
 signal  CmdCodeValid_Out_2Q: boolean;
 signal  EndPointNr:          Int_EndPointType;

 -----------------------------------------------------------------------------
 -- This is to supply certain command codes to UC handler.
 procedure send_command_code (variable CommandCode : in eleven_bits;
                              signal DataFromUC_I  : out T_UC_to_Handlers) is
 begin     
   DataFromUC_I.Address <= to_integer(CommandCode(10));
   if(CommandCode(9) = '1') then
      DataFromUC_I.read   <= true ;
   else
      DataFromUC_I.read   <= false;
   end if; 
   if(CommandCode(8) = '1') then
      DataFromUC_I.write  <=  true ; 
   else 
      DataFromUC_I.write  <= false;
   end if;     
   DataFromUC_I.Data <= CommandCode(7 DOWNTO 0);           
 end send_command_code ;
------------------------------------------------------------------------------ 

begin
 
 -- initialising the ring
 DataToUC_out <= HandlersToUCDefault;  
 EndTransfer_Cmd <= EndTransfer_Cmd_I;
 Rx_N_data <= Rx_N_data_i;
 Read         <=  Read_I ;
 DataFromUC   <=  DataFromUC_I ;
 trans_enable <= trans_enable_I;
 USBEp0Intr_Set  <= '1' when DH_interrupt_Ep0 else '0';
 USBEp1Intr_Set  <= '1' when DH_interrupt_Ep1 else '0';
 USBEp2Intr_Set  <= '1' when DH_interrupt_Ep2 else '0';
 USBEp3Intr_Set  <= '1' when DH_interrupt_Ep3 else '0';
 USBEp4Intr_Set  <= '1' when DH_interrupt_Ep4 else '0';
 USBEp5Intr_Set  <= '1' when DH_interrupt_Ep5 else '0';
 USBEp6Intr_Set  <= '1' when DH_interrupt_Ep6 else '0';
 USBEp7Intr_Set  <= '1' when DH_interrupt_Ep7 else '0';
 USBDevIntr_Set  <= '1' when DH_interrupt_Dev else '0';
 
 FullBuffer_UC  <= EPBufferInfo.Full;
 USBToggleBuffer <= EPBufferInfo.USBToggle;
 UCToggleBuffer <= EPBufferInfo.UCToggle;
 RxError <= RxError_SIE;
 PI_IsoToggle <= TM_IsoToggle;
 CmdAccept <= CmdAccept_I;
 CmdDataValid <= CmdDataValid_I;
 reg_ram_tag  <= uc_to_pi.endpoint;
 
 process(FsClk, reset_n) 
 
   variable  DataToSystem: byte;
   variable  OutEndPoint: Int_EndPointType;
   variable  ValidData: boolean;
   variable  CommandCode: eleven_bits;	
   variable  CommandFromSystem: eleven_bits;
   variable  count: integer range 0 to 4;

 begin
     -- asynchrnous reset for all registers.
     if(reset_n = '0') then 
        ValidData    := false;
        DataToSystem := (others => '0');
        EndPointNr   <= 0;
        EndTransfer_Cmd_I <= '0'; 
        trans_enable_I <= '0' ;
        Read_I <= '0';
        Read_4T <= '0';
        data_out <= (others=>'0'); 
        count_state <= 0;
        DataToUC_Buffer <= (others => '0');
        DataFromUC_I.write <= false;
        DataFromUC_I.read <= false;
        DataFromUC_I.address <= 1;
        DataFromUC_I.Data <= to_unsigned(0,8);
        pi_to_uc.rx_data <= (others => '0');
        pi_to_uc.endpoint <= 0;
        pi_to_uc.data_ready <= false;
        DatatoUC_Buffer_Rdy <= false;
        ReadCmdData <= false;
        CommandCode(10 downto 0) := "00000000000";
        N_Data_EP <= (others => '0');
        CmdDecode <= false;
        CmdAccept_I <= false;
        CmdDataValid_I <= false;
        reg_ram_read <= '0';
        CmdCodeValid_Out_Q <= false;
        if_busy_Q <= false;
        read_req_Q <= '0';
        read_req_2Q <= '0';
        ReadNData <= false;
        OutEndpoint := 0;
        CommandFromSystem := (others => '0');
        Count := 0;
	Rx_N_Data_i <= 0;
	CmdCodeValid_Out_2Q <= false;
	CommandData <= (others => '0');
        End_Transfer <= '0';
	
     elsif (FsClk'event AND FsClk = '1') then 

        -- Transferring Data to the system . The core(uc_handler block) assert 
        -- 'sie_write' signal when it has to transfer data. The setup command 
        -- is passed to the the system through interrupt and Data through  Ram. 
        -- There is one clock cycle introduced in the pi_handler.

        -- Reset for Read_I signal. 
        if(Read_I = '1') then
           Read_I <= '0';
        end if;
        -- reset for trans_enable_I ;
        if(trans_enable_I = '1') then
           trans_enable_I <= '0';
        end if;
	if(CmdAccept_I) then
	    CmdAccept_I <= false;
        end if;
        -- Reset for EndTransfer_Cmd_I
	if(EndTransfer_Cmd_I = '1') then
	   EndTransfer_Cmd_I <= '0';
        end if;
        if(DataFromUC_I.read = true) then
           DataFromUC_I.read <= false;
        end if;
        if(DataFromUC_I.write = true) then
           DataFromUC_I.write <= false;
        end if;

        -- start receiving the Data from UC Handler
        if(sie_write = '1') then
           ValidData     := true;
           DataToSystem  := uc_to_pi.rx_data;
	   OutEndPoint   := uc_to_pi.endpoint;
        end if;
	-- receive command data from UC Handler
        if(DataToUC_In.Ready) then
           DataToUC_Buffer <= DataToUC_In.Data;
	   DataToUC_Buffer_Rdy <= true;
        end if;
        -- send data to gif when GIF is not busy and data is valid
        -- assert trans_enable_I high
        if_busy_Q <= if_busy;
        if(ValidData AND (NOT if_busy_Q)) then 
              data_out <= DataToSystem;
              trans_enable_I <= '1';
              -- see whether data corresponds to slave or dma endpoints
	      EP_number <= OutEndPoint;
              ValidData  := false;
        end if;
        -- send command data to GIF 
	if(DataToUC_Buffer_Rdy and ReadCmdData) then
           if(count_state = 0) then
              EndTransfer_Cmd_I <= '0';
              count_state <= 1;
           elsif(count_state = 1) then
	      CommandData <= DataToUC_Buffer;
	      CmdDataValid_I   <= TRUE;
              count_state <= 2;
           elsif(count_state = 2) then
              EndTransfer_Cmd_I <= '1';
              count_state <= 0;
              DataToUC_Buffer_Rdy <= false;
	      ReadCmdData <= false;
	      CmdDataValid_I   <= FALSE;
           end if;
        end if;  
              
        -- Seperate command channel to recieve the commands for uC
        CmdCodeValid_Out_Q <= CmdCodeValid_Out;
        CmdCodeValid_Out_2Q <= CmdCodeValid_Out_Q;     
        if(not CmdCodeValid_Out_2Q and CmdCodeValid_Out_Q) then
	   CommandFromSystem := CommandCodeChannel;
	   CmdAccept_I <= true;
           CmdDecode   <= true;
        end if;
	if(CmdDecode) then
           CommandCode(10 DOWNTO 8) := CommandFromSystem(2 DOWNTO 0);
	   if(CommandCode(10 downto 8) = "010") then
	      ReadCmdData <= true;
           else
           ReadCmdData <= false;
           end if;
           CommandCode(7 DOWNTO 0) := CommandFromSystem(10 downto 3);
           send_command_code(CommandCode,DataFromUC_I);
           CmdDecode  <= false;
        end if;                  
        
        -- Handling of IN transfer        
        if(start_in_transfer = '1') then
          EndpointNr <= uc_to_pi.endpoint;
          ReadNData <= true;
          reg_ram_read <= '1';
        else
          reg_ram_read <= '0';
        end if;
        -- Delay Read (which is a pulse) one clock before sending it to GIF
        -- This is done to be sure that the GIF reads the correct EndpointNr
        Read_i <= Sie_Read;
        -- Synchronise read_req (twice to make sure data_in and N_Data are
        -- stable when Read_Req_2Q becomes true)
        read_req_Q <= read_req;
        read_req_2Q <= read_req_Q;
        
        -- Wait 4 cycles for data to become stable
        if(Read_i = '1') then
          count := 4;
        end if;
        if(count /= 0) then
          count := count -1;          
        end if;
        if(count = 1) then
          Read_4T <= '1';
        end if;
        -- Send data to uc_handler
        if(Read_4T = '1' and read_req_2Q = '1') then
           pi_to_uc.rx_data <= Data_In ;
           pi_to_uc.endpoint <= EndpointNr;
           pi_to_uc. data_ready <= TRUE;
           Read_4T <= '0';
        else
           pi_to_uc. data_ready <= FALSE;
        end if;

        if(ReadNdata and read_req_2Q = '1') then
           N_Data_EP <= TxDest_NData;
           ReadNData <= false;
        end if;

        if(SIE_EndTransfer = '1') then 
           N_Data_EP <= (others => '0');
        end if;
        
        if(SIE_EndTransfer = '1') then
           End_Transfer <= '1';
           if((RxError_SIE = false) or (dma_endp_iso(uc_to_pi.endpoint))) then
              Rx_N_data_i <= SIE_N_Data;
           else
              Rx_N_data_i <= 0;
           end if;
        else
           Rx_N_data_i <=  Rx_N_data_i;
           End_Transfer <= '0';
        end if;

     end if;
 end PROCESS;
end rtl;