usb_new_tx_sf_dpdm_rtl.vhdl

来自「usb rtl code, to fpga or asic」· VHDL 代码 · 共 49 行

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---- File >>> usb_new_tx_sf_dpdm_rtl.vhdl 
---- Iden >>>							970529-14:36:08
----
---- Project:		USB Development
---- Customer:		Philips_ITCL
----
---- Module:		architecture RTL of entity TX_SF_DPDM
---- Written by:	Usb User (e-mail: [e-mail])
----			Easics nv
----			Kapeldreef 60
----			B-3001	Leuven
----			Belgium
----			Tel [phone]
----			Fax [phone]
----			e-mail: [e-mail]
----
---- Creation Date:	Thu, 29 May 1997
----
---- Purpose:
----
---- Revision history:
----
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library work;
use work.PCK_GENERAL.all;
use work.PCK_USB.all;
use work.PCK_SETUP.all;
use work.PCK_CONFIGURATION.all;


architecture RTL of TX_SF_DPDM is
begin

UP_DP <= conv_active_high(
  (SIE_TxLogValue = USB_LOG_J and GetDeviceSpeed(ConfigArray) = USB_FULL_SPEED) or 
  (SIE_TxLogValue = USB_LOG_K and GetDeviceSpeed(ConfigArray) = USB_LOW_SPEED) or 
  (SIE_TxLogValue = USB_LOG_SE1_OR_Z));
UP_DM <= conv_active_high(
  (SIE_TxLogValue = USB_LOG_K and GetDeviceSpeed(ConfigArray) = USB_FULL_SPEED) or 
  (SIE_TxLogValue = USB_LOG_J and GetDeviceSpeed(ConfigArray) = USB_LOW_SPEED) or 
  (SIE_TxLogValue = USB_LOG_SE1_OR_Z));
end RTL;