📄 dds.fit.rpt
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+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 0.76) ; Number of LABs (Total = 21) ;
+------------------------------------+------------------------------+
; 1 Clock ; 12 ;
; 1 Clock enable ; 2 ;
; 1 Sync. clear ; 1 ;
; 1 Sync. load ; 1 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 7.33) ; Number of LABs (Total = 21) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 12 ;
; 11 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 3.71) ; Number of LABs (Total = 21) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 6 ;
; 2 ; 4 ;
; 3 ; 3 ;
; 4 ; 3 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 2 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 6.71) ; Number of LABs (Total = 21) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 5 ;
; 5 ; 1 ;
; 6 ; 2 ;
; 7 ; 0 ;
; 8 ; 2 ;
; 9 ; 2 ;
; 10 ; 0 ;
; 11 ; 2 ;
; 12 ; 1 ;
; 13 ; 1 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
+---------------------------------------------+------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Oct 16 15:21:58 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dds -c dds
Info: Selected device EPM240T100C5 for design "dds"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 14
Info: Automatically promoted some destinations of signal "cp_65k" to use Global clock
Info: Destination "cp_65k" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "cp_1k" to use Global clock
Info: Destination "cp_1k" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 11.429 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y2; Fanout = 38; REG Node = 'dds_add[12]'
Info: 2: + IC(1.557 ns) + CELL(0.200 ns) = 1.757 ns; Loc. = LAB_X7_Y2; Fanout = 1; COMB Node = 'Mux33~351'
Info: 3: + IC(2.647 ns) + CELL(0.200 ns) = 4.604 ns; Loc. = LAB_X5_Y1; Fanout = 1; COMB Node = 'Mux33~352'
Info: 4: + IC(1.070 ns) + CELL(0.511 ns) = 6.185 ns; Loc. = LAB_X6_Y1; Fanout = 1; COMB Node = 'Mux33~354'
Info: 5: + IC(0.440 ns) + CELL(0.740 ns) = 7.365 ns; Loc. = LAB_X6_Y1; Fanout = 1; COMB Node = 'data~466'
Info: 6: + IC(1.742 ns) + CELL(2.322 ns) = 11.429 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'data[0]'
Info: Total cell delay = 3.973 ns ( 34.76 % )
Info: Total interconnect delay = 7.456 ns ( 65.24 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 8% of the available device resources. Peak interconnect usage is 8%
Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin cs has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Processing ended: Tue Oct 16 15:22:01 2007
Info: Elapsed time: 00:00:04
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/yang/yl_vhdl/epm240_example/dds/dds.fit.smsg.
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