📄 ar320240.h
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//----------------------------------------------------------------------------
//
// Copyright (c) SHANGHAI HANGHONG Hi-Te LTD CORP.
// All rights reserved.
//
// This is the header file for 256 color LCD Ar320240.
//
// History Ver 2003/8/22 Start
//----------------------------------------------------------------------------
// Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz)
#define true 1
#define false 0
//REGISTER_OFFSET points to the starting address of the S1D13706 registers
#define REGISTER_OFFSET 0x400000
//DISP_MEM_OFFSET points to the starting address of the display buffer memery
#define DISP_MEM_OFFSET 0x440000
//DISP_MEM_SIZE is the size of S1D13706'S display buffer memery: 80K SRAM
#define DISP_MEM_SIZE 0x14000
#define LCD_POWERDOWN_TIME 1200 /*Time before LCD loses power ( millisecond )*/
#define LCD_POWERUP_TIME 50 /*Time before LCD gets power (millisecond )*/
#define S1D_DISPLAY_WIDTH 320
#define S1D_DISPLAY_HEIGHT 240
#define S1D_ONE_LINE_BYTES_NUMBER 320
#define S1D_ONE_LINE_SHORT_NUMBER 160
#define S1D_DISPLAY_BPP 8
#define S1D_PHYSICAL_VMEM_ADDR 0x00000000L
#define S1D_PHYSICAL_VMEM_SIZE 0x14000L
#define S1D_PHYSICAL_REG_ADDR 0x00000000L
#define S1D_PHYSICAL_REG_SIZE 0x100
#define S1D_DISPLAY_PCLK 6250
#define S1D_PALETTE_SIZE 256
#define S1D_REGDELAYOFF 0xFFFE
#define S1D_REGDELAYON 0xFFFF
//S1D13706 register name and offset address
#define REG_REVISION_CODE 0x00
#define REG_BCLK_MCLK_CONFIG 0x04
#define REG_PCLK_CONFIG 0x05
#define REG_PANEL_TYPE 0x10
#define REG_MODE_RATE 0x11
#define REG_HORIZ_TOTAL 0x12
#define REG_HDP 0x14
#define REG_HDP_START_POS0 0x16
#define REG_HDP_START_POS1 0x17
#define REG_VERT_TOTAL0 0x18
#define REG_VERT_TOTAL1 0x19
#define REG_VDP0 0x1c
#define REG_VDP1 0x1d
#define REG_VDP_START_POS0 0x1e
#define REG_VDP_START_POS1 0x1f
#define REG_HSYNC_PULSE_WIDTH 0x20
#define REG_HSYNC_PULSE_START_POS0 0x22
#define REG_HSYNC_PULSE_START_POS1 0x23
#define REG_VSYNC_PULSE_WIDTH 0x24
#define REG_VSYNC_PULSE_START_POS0 0x26
#define REG_VSYNC_PULSE_START_POS1 0x27
#define REG_DISPLAY_MODE 0x70
#define REG_SPECIAL_EFFECTS 0x71
#define REG_MAIN_WIN_DISP_START_ADDR0 0x74
#define REG_MAIN_WIN_DISP_START_ADDR1 0x75
#define REG_MAIN_WIN_DISP_START_ADDR2 0x76
#define REG_MAIN_WIN_ADDR_OFFSET0 0x78
#define REG_MAIN_WIN_ADDR_OFFSET1 0x79
#define REG_SUB_WIN_DISP_START_ADDR0 0x7C
#define REG_SUB_WIN_DISP_START_ADDR1 0x7D
#define REG_SUB_WIN_DISP_START_ADDR2 0x7E
#define REG_SUB_WIN_ADDR_OFFSET0 0x80
#define REG_SUB_WIN_ADDR_OFFSET1 0x81
#define REG_SUB_WIN_X_START_POS0 0x84
#define REG_SUB_WIN_X_START_POS1 0x85
#define REG_SUB_WIN_Y_START_POS0 0x88
#define REG_SUB_WIN_Y_START_POS1 0x89
#define REG_SUB_WIN_X_END_POS0 0x8C
#define REG_SUB_WIN_X_END_POS1 0x8D
#define REG_SUB_WIN_Y_END_POS0 0x90
#define REG_SUB_WIN_Y_END_POS1 0x91
#define REG_POWER_SAVE_CONFIG 0xA0
#define REG_CPU_ACCESS_CONFIG 0xA1
#define REG_SOFTWARE_RESET 0xA2
#define REG_BIG_ENDIAN_SUPPORT 0xA3
#define REG_CLR_SCRATCH_PAD0 0xA4
#define REG_CLR_SCRATCH_PAD1 0xA5
#define REG_GPIO_CONFIG0 0xA8
#define REG_GPIO_CONFIG1 0xA9
#define REG_GPIO_STATUS_CONFIG0 0xAC
#define REG_GPIO_STATUS_CONFIG1 0xAD
#define REG_PWM_CV_CLK_CONTROL 0xB0
#define REG_PWM_CV_CLK_CONFIG 0xB1
#define REG_CV_CLK_BURST_LENGTH 0xB2
#define REG_PWM_CLK_DUTY_CYCLE 0xB3
unsigned char *ucpRegBaseAddr = (unsigned char *)REGISTER_OFFSET;
unsigned char *ucpMemBaseAddr = (unsigned char *)DISP_MEM_OFFSET;
unsigned short *uspMemBaseAddr = (unsigned short*)DISP_MEM_OFFSET;
#define MACRO_ENABLE_BLANK_DISPLAY() { *(ucpRegBaseAddr + REG_DISPLAY_MODE ) |= 0x80; }
#define MACRO_DISABLE_BLANK_DISPLAY() { *(ucpRegBaseAddr + REG_DISPLAY_MODE ) &= ~0x80; }
#define MACRO_ENABLE_LCD_PANEL() { *(ucpRegBaseAddr + REG_GPIO_STATUS_CONFIG0) |= 0x10; }
#define MACRO_DISABLE_LCD_PANEL() { *(ucpRegBaseAddr + REG_GPIO_STATUS_CONFIG0) &= ~0x10; }
typedef struct RegInitItem
{
unsigned short S1D_INDEX;
unsigned char S1D_VALUE;
}REG_INIT_ITEM;
REG_INIT_ITEM S1D13706REG[] = //register offset address
{
{ REG_BCLK_MCLK_CONFIG ,0x00 },// 0x04
{ REG_PCLK_CONFIG ,0x12 },// 0x05
{ REG_PANEL_TYPE ,0xD0 },// 0x10
{ REG_MODE_RATE ,0x00 },// 0x11
{ REG_HORIZ_TOTAL ,0x2B },// 0x12
{ REG_HDP ,0x27 },// 0x14
{ REG_HDP_START_POS0 ,0x00 },// 0x16
{ REG_HDP_START_POS1 ,0x00 },// 0x17
{ REG_VERT_TOTAL0 ,0xFA },// 0x18
{ REG_VERT_TOTAL1 ,0x00 },// 0x19
{ REG_VDP0 ,0xEF },// 0x1c
{ REG_VDP1 ,0x00 },// 0x1d
{ REG_VDP_START_POS0 ,0x00 },// 0x1e
{ REG_VDP_START_POS1 ,0x00 },// 0x1f
{ REG_HSYNC_PULSE_WIDTH ,0x87 },// 0x20
{ REG_HSYNC_PULSE_START_POS0 ,0x00 },// 0x22
{ REG_HSYNC_PULSE_START_POS1 ,0x00 },// 0x23
{ REG_VSYNC_PULSE_WIDTH ,0x80 },// 0x24
{ REG_VSYNC_PULSE_START_POS0 ,0x01 },// 0x26
{ REG_VSYNC_PULSE_START_POS1 ,0x00 },// 0x27
{ REG_DISPLAY_MODE ,0x83 },// 0x70
{ REG_SPECIAL_EFFECTS ,0x00 },// 0x71
{ REG_MAIN_WIN_DISP_START_ADDR0 ,0x00 },// 0x74
{ REG_MAIN_WIN_DISP_START_ADDR1 ,0x00 },// 0x75
{ REG_MAIN_WIN_DISP_START_ADDR2 ,0x00 },// 0x76
{ REG_MAIN_WIN_ADDR_OFFSET0 ,0x50 },// 0x78
{ REG_MAIN_WIN_ADDR_OFFSET1 ,0x00 },// 0x79
{ REG_SUB_WIN_DISP_START_ADDR0 ,0x00 },// 0x7c
{ REG_SUB_WIN_DISP_START_ADDR1 ,0x00 },// 0x7d
{ REG_SUB_WIN_DISP_START_ADDR2 ,0x00 },// 0x7e
{ REG_SUB_WIN_ADDR_OFFSET0 ,0x50 },// 0x80
{ REG_SUB_WIN_ADDR_OFFSET1 ,0x00 },// 0x81
{ REG_SUB_WIN_X_START_POS0 ,0x00 },// 0x84
{ REG_SUB_WIN_X_START_POS1 ,0x00 },// 0x85
{ REG_SUB_WIN_Y_START_POS0 ,0x00 },// 0x88
{ REG_SUB_WIN_Y_START_POS1 ,0x00 },// 0x89
{ REG_SUB_WIN_X_END_POS0 ,0x4F },// 0x8c
{ REG_SUB_WIN_X_END_POS1 ,0x00 },// 0x8d
{ REG_SUB_WIN_Y_END_POS0 ,0xEF },// 0x90
{ REG_SUB_WIN_Y_END_POS1 ,0x00 },// 0x91
{ REG_POWER_SAVE_CONFIG ,0x00 },// 0xa0
{ REG_CPU_ACCESS_CONFIG ,0x00 },// 0xa1
{ REG_SOFTWARE_RESET ,0x00 },// 0xa2
{ REG_BIG_ENDIAN_SUPPORT ,0x00 },// 0xa3
{ REG_CLR_SCRATCH_PAD0 ,0x00 },// 0xa4
{ REG_CLR_SCRATCH_PAD1 ,0x00 },// 0xa5
{ REG_GPIO_CONFIG0 ,0x00 },// 0xa8
{ REG_GPIO_CONFIG1 ,0x80 },// 0xa9
{ REG_GPIO_STATUS_CONFIG0 ,0x00 },// 0xac
{ REG_GPIO_STATUS_CONFIG1 ,0x00 },// 0xad
{ REG_PWM_CV_CLK_CONTROL ,0x00 },// 0xb0
{ REG_PWM_CV_CLK_CONFIG ,0x00 },// 0xb1
{ REG_CV_CLK_BURST_LENGTH ,0x00 },// 0xb2
{ REG_PWM_CLK_DUTY_CYCLE ,0x00 } // 0xb3
};
unsigned char LUT8_Color[256 *3] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0xbf, 0x00, 0x00, 0xff,
0x00, 0x20, 0x00, 0x00, 0x20, 0x40, 0x00, 0x20, 0xbf, 0x00, 0x20, 0xff,
0x00, 0x40, 0x00, 0x00, 0x40, 0x40, 0x00, 0x40, 0xbf, 0x00, 0x40, 0xff,
0x00, 0x60, 0x00, 0x00, 0x60, 0x40, 0x00, 0x60, 0xbf, 0x00, 0x60, 0xff,
//
0x00, 0x9f, 0x00, 0x00, 0x9f, 0x40, 0x00, 0x9f, 0xbf, 0x00, 0x9f, 0xff,
0x00, 0xbf, 0x00, 0x00, 0xbf, 0x40, 0x00, 0xbf, 0xbf, 0x00, 0xbf, 0xff,
0x00, 0xdf, 0x00, 0x00, 0xdf, 0x40, 0x00, 0xdf, 0xbf, 0x00, 0xdf, 0xff,
0x00, 0xff, 0x00, 0x00, 0xff, 0x40, 0x00, 0xff, 0xbf, 0x00, 0xff, 0xff,
//
0x20, 0x00, 0x00, 0x20, 0x00, 0x40, 0x20, 0x00, 0xbf, 0x20, 0x00, 0xff,
0x20, 0x20, 0x00, 0x20, 0x20, 0x40, 0x20, 0x20, 0xbf, 0x20, 0x20, 0xff,
0x20, 0x40, 0x00, 0x20, 0x40, 0x40, 0x20, 0x40, 0xbf, 0x20, 0x40, 0xff,
0x20, 0x60, 0x00, 0x20, 0x60, 0x40, 0x20, 0x60, 0xbf, 0x20, 0x60, 0xff,
//
0x20, 0x9f, 0x00, 0x20, 0x9f, 0x40, 0x20, 0x9f, 0xbf, 0x20, 0x9f, 0xff,
0x20, 0xbf, 0x00, 0x20, 0xbf, 0x40, 0x20, 0xbf, 0xbf, 0x20, 0xbf, 0xff,
0x20, 0xdf, 0x00, 0x20, 0xdf, 0x40, 0x20, 0xdf, 0xbf, 0x20, 0xdf, 0xff,
0x20, 0xff, 0x00, 0x20, 0xff, 0x40, 0x20, 0xff, 0xbf, 0x20, 0xff, 0xff,
//
0x40, 0x00, 0x00, 0x40, 0x00, 0x40, 0x40, 0x00, 0xbf, 0x40, 0x00, 0xff,
0x40, 0x20, 0x00, 0x40, 0x20, 0x40, 0x40, 0x20, 0xbf, 0x40, 0x20, 0xff,
0x40, 0x40, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0xbf, 0x40, 0x40, 0xff,
0x40, 0x60, 0x00, 0x40, 0x60, 0x40, 0x40, 0x60, 0xbf, 0x40, 0x60, 0xff,
//
0x40, 0x9f, 0x00, 0x40, 0x9f, 0x40, 0x40, 0x9f, 0xbf, 0x40, 0x9f, 0xff,
0x40, 0xbf, 0x00, 0x40, 0xbf, 0x40, 0x40, 0xbf, 0xbf, 0x40, 0xbf, 0xff,
0x40, 0xdf, 0x00, 0x40, 0xdf, 0x40, 0x40, 0xdf, 0xbf, 0x40, 0xdf, 0xff,
0x40, 0xff, 0x00, 0x40, 0xff, 0x40, 0x40, 0xff, 0xbf, 0x40, 0xff, 0xff,
//
0x60, 0x00, 0x00, 0x60, 0x00, 0x40, 0x60, 0x00, 0xbf, 0x60, 0x00, 0xff,
0x60, 0x20, 0x00, 0x60, 0x20, 0x40, 0x60, 0x20, 0xbf, 0x60, 0x20, 0xff,
0x60, 0x40, 0x00, 0x60, 0x40, 0x40, 0x60, 0x40, 0xbf, 0x60, 0x40, 0xff,
0x60, 0x60, 0x00, 0x60, 0x60, 0x40, 0x60, 0x60, 0xbf, 0x60, 0x60, 0xff,
//
0x60, 0x9f, 0x00, 0x60, 0x9f, 0x40, 0x60, 0x9f, 0xbf, 0x60, 0x9f, 0xff,
0x60, 0xbf, 0x00, 0x60, 0xbf, 0x40, 0x60, 0xbf, 0xbf, 0x60, 0xbf, 0xff,
0x60, 0xdf, 0x00, 0x60, 0xdf, 0x40, 0x60, 0xdf, 0xbf, 0x60, 0xdf, 0xff,
0x60, 0xff, 0x00, 0x60, 0xff, 0x40, 0x60, 0xff, 0xbf, 0x60, 0xff, 0xff,
//
0x9f, 0x00, 0x00, 0x9f, 0x00, 0x40, 0x9f, 0x00, 0xbf, 0x9f, 0x00, 0xff,
0x9f, 0x20, 0x00, 0x9f, 0x20, 0x40, 0x9f, 0x20, 0xbf, 0x9f, 0x20, 0xff,
0x9f, 0x40, 0x00, 0x9f, 0x40, 0x40, 0x9f, 0x40, 0xbf, 0x9f, 0x40, 0xff,
0x9f, 0x60, 0x00, 0x9f, 0x60, 0x40, 0x9f, 0x60, 0xbf, 0x9f, 0x60, 0xff,
//
0x9f, 0x9f, 0x00, 0x9f, 0x9f, 0x40, 0x9f, 0x9f, 0xbf, 0x9f, 0x9f, 0xff,
0x9f, 0xbf, 0x00, 0x9f, 0xbf, 0x40, 0x9f, 0xbf, 0xbf, 0x9f, 0xbf, 0xff,
0x9f, 0xdf, 0x00, 0x9f, 0xdf, 0x40, 0x9f, 0xdf, 0xbf, 0x9f, 0xdf, 0xff,
0x9f, 0xff, 0x00, 0x9f, 0xff, 0x40, 0x9f, 0xff, 0xbf, 0x9f, 0xff, 0xff,
//
0xbf, 0x00, 0x00, 0xbf, 0x00, 0x40, 0xbf, 0x00, 0xbf, 0xbf, 0x00, 0xff,
0xbf, 0x20, 0x00, 0xbf, 0x20, 0x40, 0xbf, 0x20, 0xbf, 0xbf, 0x20, 0xff,
0xbf, 0x40, 0x00, 0xbf, 0x40, 0x40, 0xbf, 0x40, 0xbf, 0xbf, 0x40, 0xff,
0xbf, 0x60, 0x00, 0xbf, 0x60, 0x40, 0xbf, 0x60, 0xbf, 0xbf, 0x60, 0xff,
//
0xbf, 0x9f, 0x00, 0xbf, 0x9f, 0x40, 0xbf, 0x9f, 0xbf, 0xbf, 0x9f, 0xff,
0xbf, 0xbf, 0x00, 0xbf, 0xbf, 0x40, 0xbf, 0xbf, 0xbf, 0xbf, 0xbf, 0xff,
0xbf, 0xdf, 0x00, 0xbf, 0xdf, 0x40, 0xbf, 0xdf, 0xbf, 0xbf, 0xdf, 0xff,
0xbf, 0xff, 0x00, 0xbf, 0xff, 0x40, 0xbf, 0xff, 0xbf, 0xbf, 0xff, 0xff,
//
0xdf, 0x00, 0x00, 0xdf, 0x00, 0x40, 0xdf, 0x00, 0xbf, 0xdf, 0x00, 0xff,
0xdf, 0x20, 0x00, 0xdf, 0x20, 0x40, 0xdf, 0x20, 0xbf, 0xdf, 0x20, 0xff,
0xdf, 0x40, 0x00, 0xdf, 0x40, 0x40, 0xdf, 0x40, 0xbf, 0xdf, 0x40, 0xff,
0xdf, 0x60, 0x00, 0xdf, 0x60, 0x40, 0xdf, 0x60, 0xbf, 0xdf, 0x60, 0xff,
//
0xdf, 0x9f, 0x00, 0xdf, 0x9f, 0x40, 0xdf, 0x9f, 0xbf, 0xdf, 0x9f, 0xff,
0xdf, 0xbf, 0x00, 0xdf, 0xbf, 0x40, 0xdf, 0xbf, 0xbf, 0xdf, 0xbf, 0xff,
0xdf, 0xdf, 0x00, 0xdf, 0xdf, 0x40, 0xdf, 0xdf, 0xbf, 0xdf, 0xdf, 0xff,
0xdf, 0xff, 0x00, 0xdf, 0xff, 0x40, 0xdf, 0xff, 0xbf, 0xdf, 0xff, 0xff,
//
0xff, 0x00, 0x00, 0xff, 0x00, 0x40, 0xff, 0x00, 0xbf, 0xff, 0x00, 0xff,
0xff, 0x20, 0x00, 0xff, 0x20, 0x40, 0xff, 0x20, 0xbf, 0xff, 0x20, 0xff,
0xff, 0x40, 0x00, 0xff, 0x40, 0x40, 0xff, 0x40, 0xbf, 0xff, 0x40, 0xff,
0xff, 0x60, 0x00, 0xff, 0x60, 0x40, 0xff, 0x60, 0xbf, 0xff, 0x60, 0xff,
//
0xff, 0x9f, 0x00, 0xff, 0x9f, 0x40, 0xff, 0x9f, 0xbf, 0xff, 0x9f, 0xff,
0xff, 0xbf, 0x00, 0xff, 0xbf, 0x40, 0xff, 0xbf, 0xbf, 0xff, 0xbf, 0xff,
0xff, 0xdf, 0x00, 0xff, 0xdf, 0x40, 0xff, 0xdf, 0xbf, 0xff, 0xdf, 0xff,
0xff, 0xff, 0x00, 0xff, 0xff, 0x40, 0xff, 0xff, 0xbf, 0xff, 0xff, 0xff
};
#define S1D_WRITE_PALETTE(p, i, r, g, b) \
{ \
((volatile unsigned char *)( p ))[ 0x0A ] = ( unsigned char )(( r )); \
((volatile unsigned char *)( p ))[ 0x09 ] = ( unsigned char )(( g )); \
((volatile unsigned char *)( p ))[ 0x08 ] = ( unsigned char )(( b )); \
((volatile unsigned char *)( p ))[ 0x0B ] = ( unsigned char )( i ); \
}
/*
#define S1D_READ_PALETTE(p,i,r,g,b) \
{ \
((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \
g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \
b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \
}*/
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