video_in.h

black-fin DSP处理器单帧图像获取程序

#ifdef EMUDMA
#include "adsp21532.h"
#endif
#ifdef BLKFNedin
#include "adsp21532.h"
#endif
#ifdef BLKFNteton
#include "defBF561.h"
#endif


#ifndef __VIDEO_IN_H__
#define __VIDEO_IN_H__
//#include "vidcodec.h"

#define ALLOW_SAME_BANK

// PPI functioning in 16-bit mode.
#define FLD_IN_CFG		0x4617
#define FLD_IN_CFG_STOP_IRQ	0x0097
#define FLD_IN_CFG_LIST_IRQ     0x7997
#ifdef BLKFNteton
#define NUM_VID_BUFFERS	    10
#else
#define NUM_VID_BUFFERS	    6
#endif

/*************** STRUCTURES DEFINITIONS **********************/
#if defined(__GNUC__) || defined(__ECC__)

// PPI side Structures
typedef struct iframe
{
  struct iframe	*nxt;
  unsigned char	*pucFramePtr;
  unsigned int	ulTS;
} ifrm_t;

typedef struct _VideoInStruct_ {
  ifrm_t	*free;                // Free frame list head
  ifrm_t	*freetail;            // Free frame list tail
  ifrm_t	*queue;               // available video frame queue head
  ifrm_t	*queuetail;           // available video frame queue tail
  ifrm_t	*current;             // The frame being written
  ifrm_t        *being_encoded;
  int		underflow_cnt;
  int 		frame_cnt;            
  int           frmleft_cnt;
  int           dma_descriptor;
  ifrm_t	iFrame[NUM_VID_BUFFERS*2];
} tVideoInStruct;

/*
int	ppi_in_frame_avail();
ifrm_t*	ppi_in_dequeue_frame();
void	ppi_in_free_frame(ifrm_t* frmptr);

int	ppi_in_init(unsigned char*,unsigned char*, vidcodec_t *);
void	ppi_in_start(vidcodec_t *);
void	ppi_in_stop(void);
*/
#endif

#endif /* __VIDEO_IN_H__ */

#define IFRAME_NXT_OFFSET		(0*4)
#define IFRAME_PTR_OFFSET		(1*4)
#define IFRAME_TS_OFFSET		(2*4)
#define IFRAME_SIZE			(3*4)

#define VIDEOIN_FREE			(0*4)
#define VIDEOIN_FREETAIL		(1*4)
#define VIDEOIN_QUEUE			(2*4)
#define VIDEOIN_QUEUETAIL		(3*4)
#define VIDEOIN_CURRENT			(4*4)
#define VIDEOIN_BEING_ENCODED		(5*4)
#define VIDEOIN_UNDERFLOW_CNT		(6*4)
#define VIDEOIN_FRM_CNT			(7*4)
#define VIDEOIN_FRMLEFT_CNT		(8*4)
#define VIDEOIN_DMA      		(9*4)
#define VIDEOIN_IFRM_OFFSET		(10*4)
#define VIDEOIN_SIZE			(10*4+IFRAME_SIZE*NUM_VID_BUFFERS*2)

#ifdef EMUDMA

#define PPI_DMA_BASE_ADDR	DMA0_NEXT_DESC_PTR
#define PPI_DMA_CONFIG 		DMA0_CONFIG	
#define PPI_DMA_NEXT_DESC_PTR   DMA0_NEXT_DESC_PTR
#define PPI_SIC_IMASK_BIT       8
#define PPI_ERR_SIC_IMASK_BIT   2
#define PPI_IMASK_BIT           9
#define PPI_ERR_IMASK_BIT       7
#define PPI_EVT                 EVT9
#define PPI_IAR_POS             0

#endif

#ifdef BLKFNedin

#define PPI_DMA_BASE_ADDR	DMA0_NEXT_DESC_PTR
#define PPI_DMA_CONFIG 		DMA0_CONFIG	
#define PPI_DMA_NEXT_DESC_PTR   DMA0_NEXT_DESC_PTR
#define PPI_SIC_IMASK_BIT       8
#define PPI_IMASK_BIT           8
#define PPI_EVT                 EVT8
#define PPI_IAR_POS             0

#endif

#ifdef BLKFNteton

#define PPI_DMA_BASE_ADDR	DMA1_0_NEXT_DESC_PTR
#define PPI_DMA_CONFIG 		DMA1_0_CONFIG	
#define PPI_DMA_NEXT_DESC_PTR   DMA1_0_NEXT_DESC_PTR
#define DMA_CONFIG_OFFSET       (DMA1_0_CONFIG - DMA1_0_NEXT_DESC_PTR)
#define DMA_IRQ_STATUS_OFFSET   (DMA1_0_IRQ_STATUS - DMA1_0_NEXT_DESC_PTR)
#define DMA_CURR_ADDR_OFFSET    (DMA1_0_CURR_ADDR - DMA1_0_NEXT_DESC_PTR)
#define DMA_START_ADDR_OFFSET   (DMA1_0_START_ADDR - DMA1_0_NEXT_DESC_PTR)
#define DMA_X_COUNT_OFFSET      (DMA1_0_X_COUNT - DMA1_0_NEXT_DESC_PTR)
#define DMA_X_MODIFY_OFFSET     (DMA1_0_X_MODIFY - DMA1_0_NEXT_DESC_PTR)
#define DMA_Y_COUNT_OFFSET      (DMA1_0_Y_COUNT - DMA1_0_NEXT_DESC_PTR)
#define DMA_Y_MODIFY_OFFSET     (DMA1_0_Y_MODIFY - DMA1_0_NEXT_DESC_PTR)


#define PPI_SIC_IMASK_BIT       11
#define PPI_IMASK_BIT           8
#define PPI_EVT                 EVT8
#define PPI_IAR_POS             12
#define SIC_IMASK               SICA_IMASK0
#define SIC_IAR1                SICA_IAR1
#define SIC_ISR                 SICA_ISR0


#define PPI_CONTROL	PPI0_CONTROL		
#define PPI_STATUS	PPI0_STATUS		
#define PPI_COUNT	PPI0_COUNT		
#define PPI_DELAY	PPI0_DELAY		
#define PPI_FRAME	PPI0_FRAME		


#define MDMA_D0_CONFIG          MDMA1_D0_CONFIG
#define MDMA_D0_CURR_DESC_PTR 	MDMA1_D0_CURR_DESC_PTR 
#define MDMA_S0_CONFIG	       	MDMA1_S0_CONFIG	       
#define MDMA_S0_CURR_DESC_PTR 	MDMA1_S0_CURR_DESC_PTR 

#define MDMA_D0_BASE_ADDR       MDMA2_D0_NEXT_DESC_PTR
#define MDMA1_D0_BASE_ADDR      MDMA1_D0_NEXT_DESC_PTR

#endif