s3c2410x.h

s3c2410的vxworksBSP

/* s3c2410x.h - HITSAT s3c2410x header file */


/*
This file contains I/O address and related constants for the HITSAT
s3c2410x board.
*/

#ifndef	INCs3c2410xh
#define	INCs3c2410xh

#ifdef __cplusplus
extern "C" {
#endif

#define TARGET_S3C2410X

/* Flash definitions */
#define FLASH_BASE		0x00000000	/* Base address of Flash part */
#define FLASH_SIZE		0x00200000 	/* Total Flash available. */
#define FLASH_WIDTH		2	  	/* One 16-bit wide parts */
#define FLASH_CHIP_WIDTH        1


/*  SDRAM area definition. */
#define SDRAM_BASE		0x30000000
#define SDRAM_SIZE		0x04000000
#define SDRAM_WIDTH		4			/* Two 16-bit wide parts */
#define SDRAM_CHIP_WIDTH	2

/* RAM base in reset memory map */
#define RESET_RAM_BASE	0x30000000

#define BUS                   BUS_TYPE_NONE

/* Signals generated from s3c2410x clock generator. */
#define s3c2410x_FCLK	200000000	/* fclk = 100MHz */
#define s3c2410x_HCLK	100000000	/* hclk = 50MHz */
#define s3c2410x_PCLK	50000000	/* pclk = 50MHz */


/* arm920t PSR */

#define FIQ_ENABLE_Bit		0x40
#define IRQ_ENABLE_Bit		0x80
#define PROCESSOR_MODE_MASK	0x1F     /* Processor Mode Mask */
#define UDF_MODE		0x1B     /* Undefine Mode(UDF) */
#define ABT_MODE		0x17     /* Abort Mode(ABT) */
#define SUP_MODE		0x13     /* Supervisor Mode (SVC) */
#define IRQ_MODE		0x12     /* Interrupt Mode (IRQ) */
#define FIQ_MODE		0x11     /* Fast Interrupt Mode (FIQ) */
#define USR_MODE		0x10     /* User Mode(USR) */

/* s3c2410x Memory Controller */
#if 0
#define rBWSCON_ADR 0x48000000

	#define DW1 (1<<4)	/* 2-bits; data bus width. 8bit:16bit:32bit = 00b:01b:10b:11b. */
	#define WS1 (0<<6)	/* 1-bit; WAIT desable when 0, WAIT enable when 1. */
	#define ST1 (0<<7)	/* 1-bit; nWBE[3..0]) when 0, nBE[3..0]) when 1. */
	#define DW2 (1<<8)
	#define WS2 (0<<10)
	#define ST2 (0<<11)
	#define DW3 (0<<12)
	#define WS3 (0<<14)
	#define ST3 (0<<15)
	#define DW4 (1<<16)
	#define WS4 (0<<18)
	#define ST4 (0<<19)
	#define DW5 (1<<20)
	#define WS5 (1<<22)
	#define ST5 (1<<23)
	#define DW6 (2<<24)
	#define WS6 (0<<26)
	#define ST6 (0<<27)
	#define DW7 (2<<28)
	#define WS7 (0<<30)
	#define ST7 (0<<31)

	#define rBWSCON_INIT_VALUE (DW1+WS1+ST1+DW2+WS2+ST2+DW3+WS3+ST3+DW4+WS4+ST4+DW5+WS5+ST5+DW6+WS6+ST6+DW7+WS7+ST7)
	/* 0x22111112 */
#endif
/*---------------------------------------sam-----------------------------------*/
#define rBWSCON_ADR 0x48000000

	#define DW1 (1<<4)	/* 2-bits; data bus width. 8bit:16bit:32bit = 00b:01b:10b:11b. */
	#define WS1 (0<<6)	/* 1-bit; WAIT desable when 0, WAIT enable when 1. */
	#define ST1 (0<<7)	/* 1-bit; nWBE[3..0]) when 0, nBE[3..0]) when 1. */
	#define DW2 (1<<8)
	#define WS2 (0<<10)
	#define ST2 (0<<11)
	#define DW3 (1<<12)
	#define WS3 (1<<14)
	#define ST3 (1<<15)
	#define DW4 (1<<16)
	#define WS4 (0<<18)
	#define ST4 (0<<19)
	#define DW5 (1<<20)
	#define WS5 (1<<22)
	#define ST5 (1<<23)
	#define DW6 (2<<24)
	#define WS6 (0<<26)
	#define ST6 (0<<27)
	#define DW7 (2<<28)
	#define WS7 (0<<30)
	#define ST7 (0<<31)

	#define rBWSCON_INIT_VALUE (DW1+WS1+ST1+DW2+WS2+ST2+DW3+WS3+ST3+DW4+WS4+ST4+DW5+WS5+ST5+DW6+WS6+ST6+DW7+WS7+ST7)
	/* 0x22111112 */

#define rBANKCON0_ADR 0x48000004
	#define PMC0 (0<<0)	/* 2-bits; Page mode = normal. */
	#define Tacp0 (0<<2)	/* 2-bits; Page mode access cycle = 2 clocks.  */
	#define Tcah0 (0<<4)	/* 2-bits; Address hold time after nGCSn = 0 clocks. */
	#define Tcoh0 (0<<6)	/* 2-bits; Chip selection hold time after nOE = 0 clocks. */
	#define Tacc0 (7<<8)	/* 3-bits; Access cycle = 14 clocks. */
	#define Tcos0 (0<<11)	/* 2-bits; Chip selection set-up time before nOE = 0 clocks. */
	#define Tacs0 (0<<13)	/* 2-bits; Address set-up time before nGCSn = 0 clocks. */

	#define rBANKCON0_INIT_VALUE (PMC0+Tacp0+Tcah0+Tcoh0+Tacc0+Tcos0+Tacs0)
	/* 0x00000700 */



#define rBANKCON3_ADR 0x48000010
	#define PMC3 (0<<0)	/* 2-bits; Page mode = normal. */
	#define Tacp3 (3<<2)	/* 2-bits; Page mode access cycle = 6 clocks. */
	#define Tcah3 (3<<4)	/* 2-bits; Address hold time after nGCSn = 1 clocks. */
	#define Tcoh3 (3<<6)	/* 2-bits; Chip selection hold time after nOE = 1 clocks. */
	#define Tacc3 (7<<8)	/* 3-bits; Access cycle = 14 clocks. */
	#define Tcos3 (3<<11)	/* 2-bits; Chip selection set-up time before nOE = 1 clocks. */
	#define Tacs3 (3<<13)	/* 2-bits; Address set-up time before nGCSn = 1 clocks. */

	#define rBANKCON3_INIT_VALUE (PMC3+Tacp3+Tcah3+Tcoh3+Tacc3+Tcos3+Tacs3)
	
#define rBANKCON5_ADR 0x48000018
	#define PMC5 (0<<0)	/* 2-bits; Page mode = normal. */
	#define Tacp5 (3<<2)	/* 2-bits; Page mode access cycle = 6 clocks. */
	#define Tcah5 (3<<4)	/* 2-bits; Address hold time after nGCSn = 1 clocks. */
	#define Tcoh5 (3<<6)	/* 2-bits; Chip selection hold time after nOE = 1 clocks. */
	#define Tacc5 (7<<8)	/* 3-bits; Access cycle = 14 clocks. */
	#define Tcos5 (3<<11)	/* 2-bits; Chip selection set-up time before nOE = 1 clocks. */
	#define Tacs5 (3<<13)	/* 2-bits; Address set-up time before nGCSn = 1 clocks. */

	#define rBANKCON5_INIT_VALUE (PMC5+Tacp5+Tcah5+Tcoh5+Tacc5+Tcos5+Tacs5)
	/* 0x00000700 */

#define rBANKCON6_ADR 0x4800001c
	#define SCAN6 (1<<0)	/* 2-bits; Column address number = 9 bits. */
	#define Trcd6 (0<<2)	/* 2-bits; RAS to CAS delay = 2 clock. */
	#define MT6 (3<<15)	/* 2-bits; Set type to SyncDRAM. */

	#define rBANKCON6_INIT_VALUE (SCAN6+Trcd6+MT6)
	/* 0x00018000 */

#define rREFRESH_ADR 0x48000024
	#define Refresh_Counter (1113<<0)	/* 11-bits; SDRAM refresh count value = 1113; */
	#define Tsrc (1<<18)			/* 2-bits; SDRAM Semi Row Cycle Time = 5 clocks. */
	#define Trp (0<<20)			/* 2-bits; SDRAM RAS pre-charge Time = 2 clocks. */
	#define TREFMD (0<<22)			/* 1-bits; SDRAM Refresh Mode is Auto-Refresh. */
	#define REFEN (1<<23)			/* 1-bits; SDRAM Refresh Enable. */

	#define rREFRESH_INIT_VALUE (Refresh_Counter+Tsrc+Trp+TREFMD+REFEN)
	/* 0x00860459 */

#define rBANKSIZE_ADR 0x48000028
	#define BK76MAP (1<<0)		/* 3-bits; Bank6..7 memory map 64M/64M. */
	#define SCLK_EN (1<<4)		/* 1-bits; SCLK is enabled only during SDRAM access cycle. */
	#define SCKE_EN (1<<5)		/* 1-bits; SDRAM power down mode enable. */
	#define BURST_EN (1<<7)		/* 1-bits; ARM core enable burst operation. */

	#define rBANKSIZE_INIT_VALUE (BK76MAP+SCLK_EN+SCKE_EN+BURST_EN)
	/* 0x000000b7 */

#define rMRSRB6_ADR 0x4800002c
	#define BL6 (0<<0)		/* 3-bits; Burst length = 1(Fixed). */
	#define BT6 (0<<3)		/* 1-bits; Burst type is sequential(Fixed). */
	#define CL6 (3<<4)		/* 3-bits; CAS latency = 3 clocks. */
	#define TM6 (0<<7)		/* 2-bits; Mode register set(Fixed). */
	#define WBL6 (0<<9)		/* 1-bits; Write burst length = Burst(Fixed). */

	#define rMRSRB6_INIT_VALUE (BL6+BT6+CL6+TM6+WBL6)
	/* 0x00000030 */

/* s3c2410x Interrupt Controller */
#define rINTMSK_ADR 0x4A000008
	#define rINTSUBMSK_ADR 0x4A00001C
	
/* s3c2410x Clock & Power Management */
#define rLOCKTIME_ADR 0x4c000000
	#define M_LTIME (0xfff<<0) 	/* 12-bits; Maxim UPLL lock time count value. */
	#define U_LTIME (0xfff<<12)	/* 12-bits; Maxim MPLL lock time count value. */

	#define rLOCKTIME_INIT_VALUE (M_LTIME+U_LTIME)
	/* 0x00ffffff */

#define rMPLLCON_ADR 0x4c000004
	#define SDIVm (0<<0)	/* 2-bits; */
	#define PDIVm (4<<4)	/* 6-bits; */
	#define MDIVm (0x5c<<12)	/* 8-bits; */

	#define rMPLLCON_INIT_VALUE (SDIVm+PDIVm+MDIVm)
	/* 0x0005c040 */

#define rCLKCON_ADR 0x4c00000c

	#define rCLKCON_INIT_VALUE 0x0043d00
	/* 0x00043d00 */

#define rCLKSLOW_ADR 0x4c000010

	#define rCLKSLOW_INIT_VALUE 0x00000084
	/* 0x00000084 */

#define rCLKDIVN_ADR 0x4c000014

	#define rCLKDIVN_INIT_VALUE 0x00000003

/* s3c2410x Watch-dog Timer */
#define rWTCON_ADR	0x53000000
	
	#define rWTCON_INIT_VALUE (0x00000000)

/* s3c2410x GPIO Contol Register */
#define rGPHCON		0x56000070
	#define MASK_GPH10(x)	(x<<20)
	#define MASK_GPH9(x)	(x<<18)
	#define MASK_GPH8(x)	(x<<16)
	#define MASK_GPH7(x)	(x<<14)
	#define MASK_GPH6(x)	(x<<12)
	#define MASK_GPH5(x)	(x<<10)
	#define MASK_GPH4(x)	(x<<8)
	#define MASK_GPH3(x)	(x<<6)
	#define MASK_GPH2(x)	(x<<4)
	#define MASK_GPH1(x)	(x<<2)
	#define MASK_GPH0(x)	(x<<0)

/* Interrupt levels */
#define s3c2410x_INT_NUM_LEVELS	32
#define s3c2410x_INT_CSR_MASK_VAL	(~((unsigned int)((1<<6)+(1<<24))))
#define s3c2410x_INT_CSR_SRCPND		(0X4a000000)
#define s3c2410x_INT_CSR_INTMOD		(0X4a000004)
#define s3c2410x_INT_CSR_INTMSK		(0X4a000008)
#define s3c2410x_INT_CSR_PRIORITY	(0x4a00000c)
#define s3c2410x_INT_CSR_INTPND		(0X4a000010)
#define s3c2410x_INT_CSR_INTOFFSET	(0x4a000014)		
#define s3c2410x_INT_CSR_SUBSRCPND	(0X4a000018)
#define s3c2410x_INT_CSR_INTSUBMSK	(0X4a00001c)
#define s3c2410x_INT_CSR_EINTSTYLE	(0x56000088)
	#define EINTSTYLE_LOW		(0)
	#define EINTSTYLE_HIGH		(1)
	#define EINTSTYLE_FALL		(2)
	#define EINTSTYLE_RISE		(4)
	#define EINTSTYLE_BOTHEDGE	(6)
	
	#define EINT0_7_STYLE	((EINTSTYLE_HIGH<<0)+(EINTSTYLE_RISE<<4)+(EINTSTYLE_FALL<<8)+(EINTSTYLE_FALL<<12)+(EINTSTYLE_LOW<<16)+(EINTSTYLE_LOW<<20)+(EINTSTYLE_LOW<<24)+(EINTSTYLE_LOW<<28))

/* EINT0 for CS8900A *//* EINT1 for EOC of TLV1543*//* EINT2 for OML_CNTL *//* EINT3 for RST_4S1 *//* EINT4 *//* EINT5 *//* EINT6 *//* EINT7 */
#define INT_LVL_EINT_0		0
#define INT_LVL_EINT_1		1
#define INT_LVL_EINT_2		2
#define INT_LVL_EINT_3		3
#define INT_LVL_EINT_4_7	4
#define INT_LVL_EINT_8_23	5
/* Reserved 6 */
#define INT_LVL_nBATT_FLT	7
#define INT_LVL_TICK		8
#define INT_LVL_WDT		9
#define INT_LVL_TIMER_0		10
#define INT_LVL_TIMER_1		11
#define INT_LVL_TIMER_2		12
#define INT_LVL_TIMER_3		13
#define INT_LVL_TIMER_4		14
#define INT_LVL_UART_2		15
#define INT_LVL_LCD		16
#define INT_LVL_DMA_0		17
#define INT_LVL_DMA_1		18
#define INT_LVL_DMA_2		19
#define INT_LVL_DMA_3		20
#define INT_LVL_SDI		21
#define INT_LVL_SPI_0		22
#define INT_LVL_UART_1		23
/* Reserved 24 */