📄 lpc2400.s
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LDR R4, =EMC_DYN_RAS_Val
STR R4, [R0, #EMC_DYN_RAS_OFS]
LDR R4, =EMC_DYN_SREX_Val
STR R4, [R0, #EMC_DYN_SREX_OFS]
LDR R4, =EMC_DYN_APR_Val
STR R4, [R0, #EMC_DYN_APR_OFS]
LDR R4, =EMC_DYN_DAL_Val
STR R4, [R0, #EMC_DYN_DAL_OFS]
LDR R4, =EMC_DYN_WR_Val
STR R4, [R0, #EMC_DYN_WR_OFS]
LDR R4, =EMC_DYN_RC_Val
STR R4, [R0, #EMC_DYN_RC_OFS]
LDR R4, =EMC_DYN_RFC_Val
STR R4, [R0, #EMC_DYN_RFC_OFS]
LDR R4, =EMC_DYN_XSR_Val
STR R4, [R0, #EMC_DYN_XSR_OFS]
LDR R4, =EMC_DYN_RRD_Val
STR R4, [R0, #EMC_DYN_RRD_OFS]
LDR R4, =EMC_DYN_MRD_Val
STR R4, [R0, #EMC_DYN_MRD_OFS]
LDR R4, =EMC_DYN_RD_CFG_Val
STR R4, [R0, #EMC_DYN_RD_CFG_OFS]
IF (EMC_DYNCS0_SETUP != 0)
LDR R4, =EMC_DYN_RASCAS0_Val
STR R4, [R0, #EMC_DYN_RASCAS0_OFS]
LDR R4, =EMC_DYN_CFG0_Val
MVN R5, #BUFEN_Const
AND R4, R4, R5
STR R4, [R0, #EMC_DYN_CFG0_OFS]
ENDIF
IF (EMC_DYNCS1_SETUP != 0)
LDR R4, =EMC_DYN_RASCAS1_Val
STR R4, [R0, #EMC_DYN_RASCAS1_OFS]
LDR R4, =EMC_DYN_CFG1_Val
MVN R5, =BUFEN_Const
AND R4, R4, R5
STR R4, [R0, #EMC_DYN_CFG1_OFS]
ENDIF
IF (EMC_DYNCS2_SETUP != 0)
LDR R4, =EMC_DYN_RASCAS2_Val
STR R4, [R0, #EMC_DYN_RASCAS2_OFS]
LDR R4, =EMC_DYN_CFG2_Val
MVN R5, =BUFEN_Const
AND R4, R4, R5
STR R4, [R0, #EMC_DYN_CFG2_OFS]
ENDIF
IF (EMC_DYNCS3_SETUP != 0)
LDR R4, =EMC_DYN_RASCAS3_Val
STR R4, [R0, #EMC_DYN_RASCAS3_OFS]
LDR R4, =EMC_DYN_CFG3_Val
MVN R5, =BUFEN_Const
AND R4, R4, R5
STR R4, [R0, #EMC_DYN_CFG3_OFS]
ENDIF
LDR R6, =1440000 ; Number of cycles to delay
Wait_0 SUBS R6, R6, #1 ; Delay ~100 ms proc clk 57.6 MHz
BNE Wait_0 ; BNE (3 cyc) + SUBS (1 cyc) = 4 cyc
LDR R4, =(NOP_CMD:OR:0x03) ; Write NOP Command
STR R4, [R0, #EMC_DYN_CTRL_OFS]
LDR R6, =2880000 ; Number of cycles to delay
Wait_1 SUBS R6, R6, #1 ; Delay ~200 ms proc clk 57.6 MHz
BNE Wait_1
LDR R4, =(PALL_CMD:OR:0x03) ; Write Precharge All Command
STR R4, [R0, #EMC_DYN_CTRL_OFS]
MOV R4, #2
STR R4, [R0, #EMC_DYN_RFSH_OFS]
MOV R6, #64 ; Number of cycles to delay
Wait_2 SUBS R6, R6, #1 ; Delay
BNE Wait_2
LDR R4, =EMC_DYN_RFSH_Val
STR R4, [R0, #EMC_DYN_RFSH_OFS]
LDR R4, =(MODE_CMD:OR:0x03) ; Write MODE Command
STR R4, [R0, #EMC_DYN_CTRL_OFS]
; Dummy read (set SDRAM Mode register)
IF (EMC_DYNCS0_SETUP != 0)
LDR R4, =DYN_MEM0_BASE
LDR R5, =(EMC_DYN_RASCAS0_Val:AND:0x00000300) ; get CAS Latency
LSR R5, #4 ; set CAS Latency (Bit4..6)
IF ((EMC_DYN_CFG0_Val:AND:0x00004000) != 0)
ORR R5, R5, #0x02 ; set burst length 4 (Bit0..2)
LSL R5, #11
ELSE
ORR R5, R5, #0x03 ; set burst length 8 (Bit0..2)
LSL R5, #12
ENDIF
ADD R4, R4, R5
LDR R4, [R4, #0]
ENDIF
IF (EMC_DYNCS1_SETUP != 0)
LDR R4, =DYN_MEM1_BASE
LDR R5, =(EMC_DYN_RASCAS1_Val:AND:0x00000300) ; get CAS Latency
LSR R5, #4 ; set CAS Latency (Bit4..6)
IF ((EMC_DYN_CFG1_Val:AND:0x00004000) != 0)
ORR R5, R5, #0x02 ; set burst length 4 (Bit0..2)
LSL R5, #11
ELSE
ORR R5, R5, #0x03 ; set burst length 8 (Bit0..2)
LSL R5, #12
ENDIF
ADD R4, R4, R5
LDR R4, [R4, #0]
ENDIF
IF (EMC_DYNCS2_SETUP != 0)
LDR R4, =DYN_MEM2_BASE
LDR R5, =(EMC_DYN_RASCAS2_Val:AND:0x00000300) ; get CAS Latency
LSR R5, #4 ; set CAS Latency (Bit4..6)
IF ((EMC_DYN_CFG2_Val:AND:0x00004000) != 0)
ORR R5, R5, #0x02 ; set burst length 4 (Bit0..2)
LSL R5, #11
ELSE
ORR R5, R5, #0x03 ; set burst length 8 (Bit0..2)
LSL R5, #12
ENDIF
ADD R4, R4, R5
LDR R4, [R4, #0]
ENDIF
IF (EMC_DYNCS3_SETUP != 0)
LDR R4, =DYN_MEM3_BASE
LDR R5, =(EMC_DYN_RASCAS3_Val:AND:0x00000300) ; get CAS Latency
LSR R5, #4 ; set CAS Latency (Bit4..6)
IF ((EMC_DYN_CFG3_Val:AND:0x00004000) != 0)
ORR R5, R5, #0x02 ; set burst length 4 (Bit0..2)
LSL R5, #11
ELSE
ORR R5, R5, #0x03 ; set burst length 8 (Bit0..2)
LSL R5, #12
ENDIF
ADD R4, R4, R5
LDR R4, [R4, #0]
ENDIF
LDR R4, =NORMAL_CMD ; Write NORMAL Command
STR R4, [R0, #EMC_DYN_CTRL_OFS]
; Enable buffer if requested by settings
IF (EMC_DYNCS0_SETUP != 0):LAND:((EMC_DYN_CFG0_Val:AND:BUFEN_Const) != 0)
LDR R4, =EMC_DYN_CFG0_Val
STR R4, [R0, #EMC_DYN_CFG0_OFS]
ENDIF
IF (EMC_DYNCS1_SETUP != 0):LAND:((EMC_DYN_CFG1_Val:AND:BUFEN_Const) != 0)
LDR R4, =EMC_DYN_CFG1_Val
STR R4, [R0, #EMC_DYN_CFG1_OFS]
ENDIF
IF (EMC_DYNCS2_SETUP != 0):LAND:((EMC_DYN_CFG2_Val:AND:BUFEN_Const) != 0)
LDR R4, =EMC_DYN_CFG2_Val
STR R4, [R0, #EMC_DYN_CFG2_OFS]
ENDIF
IF (EMC_DYNCS3_SETUP != 0):LAND:((EMC_DYN_CFG3_Val:AND:BUFEN_Const) != 0)
LDR R4, =EMC_DYN_CFG3_Val
STR R4, [R0, #EMC_DYN_CFG3_OFS]
ENDIF
LDR R6, =14400 ; Number of cycles to delay
Wait_3 SUBS R6, R6, #1 ; Delay ~1 ms @ proc clk 57.6 MHz
BNE Wait_3
ENDIF ; EMC_DYNAMIC_SETUP
; Setup Static Memory Interface
IF (EMC_STATIC_SETUP != 0)
LDR R6, =1440000 ; Number of cycles to delay
Wait_4 SUBS R6, R6, #1 ; Delay ~100 ms @ proc clk 57.6 MHz
BNE Wait_4
IF (EMC_STACS0_SETUP != 0)
LDR R4, =EMC_STA_CFG0_Val
STR R4, [R0, #EMC_STA_CFG0_OFS]
LDR R4, =EMC_STA_WWEN0_Val
STR R4, [R0, #EMC_STA_WWEN0_OFS]
LDR R4, =EMC_STA_WOEN0_Val
STR R4, [R0, #EMC_STA_WOEN0_OFS]
LDR R4, =EMC_STA_WRD0_Val
STR R4, [R0, #EMC_STA_WRD0_OFS]
LDR R4, =EMC_STA_WPAGE0_Val
STR R4, [R0, #EMC_STA_WPAGE0_OFS]
LDR R4, =EMC_STA_WWR0_Val
STR R4, [R0, #EMC_STA_WWR0_OFS]
LDR R4, =EMC_STA_WTURN0_Val
STR R4, [R0, #EMC_STA_WTURN0_OFS]
ENDIF
IF (EMC_STACS1_SETUP != 0)
LDR R4, =EMC_STA_CFG1_Val
STR R4, [R0, #EMC_STA_CFG1_OFS]
LDR R4, =EMC_STA_WWEN1_Val
STR R4, [R0, #EMC_STA_WWEN1_OFS]
LDR R4, =EMC_STA_WOEN1_Val
STR R4, [R0, #EMC_STA_WOEN1_OFS]
LDR R4, =EMC_STA_WRD1_Val
STR R4, [R0, #EMC_STA_WRD1_OFS]
LDR R4, =EMC_STA_WPAGE1_Val
STR R4, [R0, #EMC_STA_WPAGE1_OFS]
LDR R4, =EMC_STA_WWR1_Val
STR R4, [R0, #EMC_STA_WWR1_OFS]
LDR R4, =EMC_STA_WTURN1_Val
STR R4, [R0, #EMC_STA_WTURN1_OFS]
ENDIF
IF (EMC_STACS2_SETUP != 0)
LDR R4, =EMC_STA_CFG2_Val
STR R4, [R0, #EMC_STA_CFG2_OFS]
LDR R4, =EMC_STA_WWEN2_Val
STR R4, [R0, #EMC_STA_WWEN2_OFS]
LDR R4, =EMC_STA_WOEN2_Val
STR R4, [R0, #EMC_STA_WOEN2_OFS]
LDR R4, =EMC_STA_WRD2_Val
STR R4, [R0, #EMC_STA_WRD2_OFS]
LDR R4, =EMC_STA_WPAGE2_Val
STR R4, [R0, #EMC_STA_WPAGE2_OFS]
LDR R4, =EMC_STA_WWR2_Val
STR R4, [R0, #EMC_STA_WWR2_OFS]
LDR R4, =EMC_STA_WTURN2_Val
STR R4, [R0, #EMC_STA_WTURN2_OFS]
ENDIF
IF (EMC_STACS3_SETUP != 0)
LDR R4, =EMC_STA_CFG3_Val
STR R4, [R0, #EMC_STA_CFG3_OFS]
LDR R4, =EMC_STA_WWEN3_Val
STR R4, [R0, #EMC_STA_WWEN3_OFS]
LDR R4, =EMC_STA_WOEN3_Val
STR R4, [R0, #EMC_STA_WOEN3_OFS]
LDR R4, =EMC_STA_WRD3_Val
STR R4, [R0, #EMC_STA_WRD3_OFS]
LDR R4, =EMC_STA_WPAGE3_Val
STR R4, [R0, #EMC_STA_WPAGE3_OFS]
LDR R4, =EMC_STA_WWR3_Val
STR R4, [R0, #EMC_STA_WWR3_OFS]
LDR R4, =EMC_STA_WTURN3_Val
STR R4, [R0, #EMC_STA_WTURN3_OFS]
ENDIF
LDR R6, =144000 ; Number of cycles to delay
Wait_5 SUBS R6, R6, #1 ; Delay ~10 ms @ proc clk 57.6 MHz
BNE Wait_5
LDR R4, =EMC_STA_EXT_W_Val
LDR R5, =EMC_STA_EXT_W_OFS
ADD R5, R5, R0
STR R4, [R5, #0]
ENDIF ; EMC_STATIC_SETUP
ENDIF ; EMC_SETUP
; Copy Exception Vectors to Internal RAM ---------------------------------------
IF :DEF:RAM_INTVEC
ADR R8, Vectors ; Source
LDR R9, =RAM_BASE ; Destination
LDMIA R8!, {R0-R7} ; Load Vectors
STMIA R9!, {R0-R7} ; Store Vectors
LDMIA R8!, {R0-R7} ; Load Handler Addresses
STMIA R9!, {R0-R7} ; Store Handler Addresses
ENDIF
; Memory Mapping (when Interrupt Vectors are in RAM) ---------------------------
MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
IF :DEF:REMAP
LDR R0, =MEMMAP
IF :DEF:EXTMEM_MODE
MOV R1, #3
ELIF :DEF:RAM_MODE
MOV R1, #2
ELSE
MOV R1, #1
ENDIF
STR R1, [R0]
ENDIF
; Setup Stack for each mode ----------------------------------------------------
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
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