📄 mxd_sdk_api.c
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videoStreamThd = (psDemodProperty->m_sCbSetting.m_DtmbDataThrd) >> 1;
/* Init hard interrupt pin */
/* m_IntType refer to hard interrupt pin */
if( 1 == ((PDEVICE_PROPERTY_S)hDevice)->m_sDemod.m_IntType )
{
intCtrlVal = (MXD_U8)((((PDEVICE_PROPERTY_S)hDevice)->m_sDemod.m_IntType)<<1)
| (((PDEVICE_PROPERTY_S)hDevice)->m_sDemod.m_IntLevel);
DDS_WriteRegFields( hDevice,
COMMON_HIC_INT_CTRL_REG,
0x0,
2,
intCtrlVal );
}
/* clear interrupt */
DDS_WriteReg( hDevice, DTMB_TDP_INT_CLEAR_REG, 0xff );
/* unmask interrupt */
DDS_WriteReg( hDevice, DTMB_TDP_INT_MASK_REG, 0x00 );
/*
* Config HIC
*/
DDS_WriteReg( hDevice, DTMB_SDI_SDRM_START_ADDR_H_REG, (MXD_U8)(DTMB_SDI_SDRM_START_ADDR_VAL>>8) );
DDS_WriteReg( hDevice, DTMB_SDI_SDRM_START_ADDR_L_REG, (MXD_U8)DTMB_SDI_SDRM_START_ADDR_VAL );
DDS_WriteReg( hDevice, DTMB_HIC_SDRM_ROW_BADDR_H_REG, (MXD_U8)(DTMB_HIC_SDRM_ROW_BADDR_VAL>>8) );
DDS_WriteReg( hDevice, DTMB_HIC_SDRM_ROW_BADDR_L_REG, (MXD_U8)DTMB_HIC_SDRM_ROW_BADDR_VAL );
DDS_WriteReg( hDevice, DTMB_HIC_SDRM_ROW_EADDR_H_REG, (MXD_U8)(DTMB_HIC_SDRM_ROW_EADDR_VAL>>8) );
DDS_WriteReg( hDevice, DTMB_HIC_SDRM_ROW_EADDR_L_REG, (MXD_U8)DTMB_HIC_SDRM_ROW_EADDR_VAL);
DDS_WriteReg( hDevice, DTMB_HIC_DATA_THLD_H_REG, (MXD_U8)(videoStreamThd>>16) );
DDS_WriteReg( hDevice, DTMB_HIC_DATA_THLD_M_REG, (MXD_U8)(videoStreamThd>>8) );
DDS_WriteReg( hDevice, DTMB_HIC_DATA_THLD_L_REG, (MXD_U8)(videoStreamThd) );
/* Set tuner related regs */
if( 0 == psDeviceProperty->m_sTuner.m_LifOrNZif )/*the tuner is ZIF*/
{
psTunerProperty->m_IfRate = 6;
DDS_WriteReg( hDevice, DTMB_TDP_BSL_REG, 0x4d);
}
else
{
psTunerProperty->m_IfRate = 6;
DDS_WriteReg( hDevice, DTMB_TDP_BSL_REG, 0x6d);
}
switch(psTunerProperty->m_IfRate)
{
case 2:
{
ifType = (psDeviceProperty->m_sTuner.m_LifOrNZif<<2);
break;
}
case 4:
{
ifType = (psDeviceProperty->m_sTuner.m_LifOrNZif<<2)|0x1;
break;
}
case 6:
{
ifType = (psDeviceProperty->m_sTuner.m_LifOrNZif<<2)|0x2;
break;
}
default:
return MXD_RTN_FAIL;
}
DDS_WriteReg( hDevice, DTMB_TDP_IF_TYPE_REG, ifType );
DDS_WriteReg( hDevice, DTMB_TDP_RTO_INT_REG, 0x4 );
DDS_WriteReg( hDevice, DTMB_TDP_RTO_FRT_H_REG, 0x55 );
DDS_WriteReg( hDevice, DTMB_TDP_RTO_FRT_M_REG, 0x9a );
DDS_WriteReg( hDevice, DTMB_TDP_RTO_FRT_L_REG, 0xaf );
DDS_WriteReg( hDevice, COMMON_EXTERNAL_CLK_GATE_EN_REG, CLOCK_GATING_EN );
return MXD_RTN_OK;
}/* end of DTMB_InitDevice( ) */
/*!
* Start device to reception DTMB signal,begin synchronization.
*
* \param hDevice: [in] Device handle
*
* \return Return code by MXD_RTN_CODE_E enumeration.
*
* \remarks
*
*/
MXD_RTN_CODE_E MXD_API DTMB_StartDevice( IN HMXDDEV hDevice )
{
MXD_RTN_CODE_E eRtnCode = MXD_RTN_OK;
PDEVICE_PROPERTY_S psDeviceProperty;
PDEMOD_PROPERTY_S psDemodProperty;
psDeviceProperty = (PDEVICE_PROPERTY_S)hDevice;
psDemodProperty = &psDeviceProperty->m_sDemod;
DDS_WriteReg( hDevice, DTMB_TDP_DU_H_REG, (MXD_U8)(psDeviceProperty->m_DU>>16) );
DDS_WriteReg( hDevice, DTMB_TDP_DU_M_REG, (MXD_U8)(psDeviceProperty->m_DU>>8) );
DDS_WriteReg( hDevice, DTMB_TDP_DU_L_REG, (MXD_U8)(psDeviceProperty->m_DU) );
/* Set mtx table begin address */
DDS_WriteReg( hDevice, DTMB_HIC_MTX_ROW_EADDR_H_REG, (MXD_U8)(MTXTABLE_IN_SDRAM>>8) );
DDS_WriteReg( hDevice, DTMB_HIC_MTX_ROW_EADDR_L_REG, (MXD_U8)MTXTABLE_IN_SDRAM );
DDS_WriteReg( hDevice, DTMB_TDP_FO_MS_REG, 0x1);
DDS_WriteReg( hDevice, DTMB_TDP_ZSP_MS_REG, 0x08);
DDS_WriteReg( hDevice, DTMB_TDP_ZSP_IS_REG, 0x80);
DDS_WriteReg( hDevice, DTMB_TDP_Q_SCALE_REG, 0x40);
DDS_WriteReg( hDevice, DTMB_TDP_CTS_RESULT_L_REG, 0x0);
DDS_WriteReg( hDevice, DTMB_TDP_CTS_RESULT_H_REG, 0x80);
DDS_WriteReg( hDevice, DTMB_TDP_FTT_MAX_FG_L_REG, 0x0);
DDS_WriteReg( hDevice, DTMB_TDP_FTT_MAX_FG_H_REG, 0x0);
DDS_WriteReg( hDevice, DTMB_TDP_FID_PARA_REG, 0xfc);
DDS_WriteReg( hDevice, DTMB_TDP_AFLT_TYPE_REG, 0xd);
DDS_WriteReg( hDevice, DTMB_FDP_MUL_BSL_REG, 0x02);
DDS_WriteReg( hDevice, DTMB_FDP_MC_BSL_REG, 0x1);
DDS_WriteReg( hDevice, DTMB_TDP_PNUM_REG, 0x10);
DDS_WriteReg( hDevice, DTMB_TDP_SET_ZERO_RANGE_REG, 0x10);
DDS_WriteReg( hDevice, DTMB_TDP_FTT_MIN_THD_REG, 0x1);
DDS_WriteReg( hDevice, DTMB_CPE_PARA_REG, 0x09);
DDS_WriteReg( hDevice, DTMB_CPE_THD_REG, 0x30);
DDS_WriteReg( hDevice, DTMB_TDP_IQREF_REG, 0x55 );
DDS_WriteReg( hDevice, DTMB_TDP_ZSP_MS_REG, 0x08);
DDS_WriteReg( hDevice, DTMB_TDP_ZSP_IS_REG, 0x10);
if( 0x4 == psDeviceProperty->m_PnType )
{
DDS_WriteReg( hDevice, DTMB_FDP_SCALE_REG, 0xb5);
DDS_WriteReg( hDevice, DTMB_TDP_WORK_MODE_REG, 0x8 );
DDS_WriteReg( hDevice, DTMB_TDP_FTT_PARA_REG, 0xc8);
DDS_WriteReg( hDevice, DTMB_TDP_FTT_THD_REG, 0x20);
DDS_WriteReg( hDevice, DTMB_TDP_ZSP_PARA_REG, 0x18 );
}
else
{
DDS_WriteReg( hDevice, DTMB_TDP_FTT_PARA_REG, 0xc6);
DDS_WriteReg( hDevice, DTMB_TDP_FTT_THD_REG, 0x5);
DDS_WriteReg( hDevice, DTMB_FDP_SCALE_REG, 0x7a);
DDS_WriteReg( hDevice, DTMB_TDP_WORK_MODE_REG, 0x28 );
if( psDeviceProperty->m_PnType<2 )
{
DDS_WriteReg( hDevice, DTMB_TDP_ZSP_PARA_REG, 0x10 );
}
else
{
DDS_WriteReg( hDevice, DTMB_TDP_ZSP_PARA_REG, 0x1c );
}
}
/* Set para at different carrier mode */
if( DEV_MODE_DTMB_MC == psDeviceProperty->m_eDevMode )
{
DDS_WriteReg( hDevice, DTMB_FDP_MUL_BSL_REG, 0x0);
DDS_WriteReg( hDevice, DTMB_FDP_SC_DP_BSL_REG, 0x2);
DDS_WriteReg( hDevice, DTMB_FDP_CARRIER_MODE_REG, 0x2);
DDS_WriteReg( hDevice, DTMB_FDP_FDI_WORK_MODE_REG, 0x2);
}
else
{
DDS_WriteReg( hDevice, DTMB_TDP_AFLT_TYPE_REG, 0xd);
DDS_WriteReg( hDevice, DTMB_FDP_MUL_BSL_REG, 0x1);
DDS_WriteReg( hDevice, DTMB_FDP_SDIV_BSL_REG, 0xd9);
DDS_WriteReg( hDevice, DTMB_FDP_HW_DIV_THD_REG, 0x1);
DDS_WriteReg( hDevice, DTMB_FDP_SC_DP_BSL_REG, 0x2);
DDS_WriteReg( hDevice, DTMB_FDP_CARRIER_MODE_REG, 0x3);
DDS_WriteReg( hDevice, DTMB_FDP_FDI_WORK_MODE_REG, 0x3);
}
DDS_WriteReg( hDevice, DTMB_CPE_THD_REG, 0x30 );
DDS_WriteReg( hDevice, DTMB_TDP_FTT_MIN_THD_REG, 0x10 );
DDS_WriteReg( hDevice, DTMB_SDI_BYPASS_EN_REG, SDI_BYPASS_EN );
/* set fec discard threshold*/
DDS_WriteReg( hDevice, DTMB_FEC_TOTAL_ERRNUM_RES_THD_L_REG, 0xff);
DDS_WriteReg( hDevice, DTMB_FEC_TOTAL_ERRNUM_RES_THD_H_REG, 0xff);
DDS_WriteReg( hDevice, DTMB_FEC_TOTAL_ERRNUM_DIS_THD_REG, 0x5);
DDS_WriteReg( hDevice, DTMB_FEC_DISCARD_CONFIG_REG, 0x0f);
DDS_WriteReg( hDevice, DTMB_FEC_CONFIG_REG, 0x10 );
DDS_WriteReg( hDevice, DTMB_FDP_ABC_OFFSET_REG, 0x80 );
/* Added for version20080113*/
DDS_WriteReg( hDevice, DTMB_TDP_AGC_AFLT_PARA_REG, 0x73 );
DDS_WriteReg( hDevice, DTMB_TDP_CYPT_STEP_H_REG, 0x00 );
DDS_WriteReg( hDevice, DTMB_TDP_CYPT_STEP_L_REG, 0x10 );
DDS_WriteReg( hDevice, DTMB_TDP_FTT_FAIL_CNT_REG, 0x02 );
DDS_WriteReg( hDevice, DTMB_TDP_ZSP_PARA_REG, 0x10 );
DDS_WriteReg( hDevice, DTMB_TDP_CTS_RS_CONFIG_REG, 0x0 );
DDS_WriteReg( hDevice, DTMB_TDP_AGC_PARA_REG, 0xb4); /*pwm enable*/
DDS_WriteReg( hDevice, DTMB_TDP_INIT_FO_H_REG, (MXD_U8)(psDeviceProperty->m_InitFo>>16));
DDS_WriteReg( hDevice, DTMB_TDP_INIT_FO_M_REG, (MXD_U8)(psDeviceProperty->m_InitFo>>8));
DDS_WriteReg( hDevice, DTMB_TDP_INIT_FO_L_REG, (MXD_U8)(psDeviceProperty->m_InitFo));
DDS_WriteReg( hDevice, DTMB_TDP_INIT_REG, 0x1 );
return eRtnCode;
}/* end of DTMB_StartDevice( ) */
/*!
* Check whether TPS is stable, if not return fail .
*
* \param hDevice: [in] Device handle
* \param milliseconds:[in] Check the status after delay( unit: ms )
*
* \return Return code by MXD_RTN_CODE_E enumeration.
*
* \remark null
*
*/
MXD_RTN_CODE_E MXD_API DTMB_CheckTpsVal( IN HMXDDEV hDevice )
{
MXD_RTN_CODE_E eRtnCode = MXD_RTN_OK;
MXD_U8 regVal = 0;
MXD_U8 checkTpsVal;
MXD_U8 tpsSumI, tpsSumQ;
MXD_S16 tpsSumIVal,tpsSumQVal;
DDS_ReadReg( hDevice, DTMB_TDP_TPS_REG, ®Val );
/* check whether tps value is reasonalbe */
if((regVal < 0x30) && !(regVal&0x10))
{
checkTpsVal = regVal&0x0f;
if( (checkTpsVal != 0x3) &&
(checkTpsVal != 0x6) &&
(checkTpsVal != 0x9) &&
(checkTpsVal != 0xa) &&
(checkTpsVal != 0xb))
{
DDS_WriteRegFields( hDevice, DTMB_MISC_READ_FREEZE_REG, MXD_BIT3, 1, 0x1 );
DDS_ReadReg( hDevice, DTMB_TDP_TPS_SUM_I_REG, &tpsSumI );
DDS_ReadReg( hDevice, DTMB_TDP_TPS_SUM_Q_REG, &tpsSumQ );
if( tpsSumI&TDP_TPS_SUM_I_MINUS_SET )
{
tpsSumIVal = 256 - tpsSumI;
}
else
{
tpsSumIVal = tpsSumI;
}
if( tpsSumQ&TDP_TPS_SUM_Q_MINUS_SET )
{
tpsSumQVal = 256 - tpsSumQ;
}
else
{
tpsSumQVal = tpsSumQ;
}
if(( tpsSumIVal <= (tpsSumQVal*3)/4 )
|| ( tpsSumQVal <= (tpsSumIVal*3)/4 ) )
{
OAL_DebugPrint(MXD_ULTRA_TRACE, "DTMB_CheckTpsVal:: error! TPS sum I&Q is not equal !!___I:%d, Q: %d\n", tpsSumIVal, tpsSumQVal);
eRtnCode = MXD_RTN_FAIL;
}
else
{
OAL_DebugPrint(MXD_ULTRA_TRACE, "DTMB_CheckTpsVal:: OK! TPS is 0x%x\n", regVal);
return MXD_RTN_OK;
}
}
else
{
OAL_DebugPrint(MXD_ULTRA_TRACE, "DTMB_CheckTpsVal:: error! TPS is not reasonalbe__0x%x!!\n", regVal);
eRtnCode = MXD_RTN_FAIL;
}
}
return eRtnCode;
}/* end of DTMB_CheckTpsVal( ) */
/*!
* Query whether signal is locked or not. If synced, return MXD_RTN_OK, else return MXD_RTN_FAIL.
*
* \param hDevice: [in] Device handle
* \param milliseconds:[in] Check the status after delay( unit: ms )
*
* \return Return code by MXD_RTN_CODE_E enumeration.
*
* \remark null
*
*/
MXD_RTN_CODE_E MXD_API DTMB_IsSignalSynced(
IN HMXDDEV hDevice,
IN MXD_U32 milliseconds )
{
MXD_RTN_CODE_E eRtnCode = MXD_RTN_OK;
MXD_U8 regVal = 0;
eRtnCode = DTMB_IsTpsOk( hDevice, milliseconds );
if( MXD_SUCCESS(eRtnCode) )
{
eRtnCode = DTMB_CheckTpsVal( hDevice );
return eRtnCode;
}
OAL_DebugPrint(MXD_ULTRA_TRACE, "DTMB_IsSignalSynced:: err! TPS is 0x%x\n",regVal);
return MXD_RTN_FAIL;
}/* end of DTMB_IsSignalSynced( ) */
/*!
* Start DTMB data reception.
*
* \param hDevice: [in] Device handle
* \param tpsId: [in] TPS to be configuated for demodulation.
*
* \return Return code by MXD_RTN_CODE_E enumeration.
*
* \remark null
*
*/
MXD_RTN_CODE_E MXD_API DTMB_StartStream(
IN HMXDDEV hDevice,
IN MXD_U8 tpsId )
{
MXD_U8 qamBSL[16] = { 0x24,0x2c,0x24,0x24,
0x22,0x23,0x24,0x23,
0x23,0x24,0x24,0x24,
0x24,0x2c,0x2d,0x2d};
MXD_U8 iterNum[3][5] = {
{0xeb,0xd2,0xca,0xd2,0xeb},
{0xeb,0xd4,0xcc,0xd2,0xeb},
{0xea,0xd3,0xca,0xcd,0xeb}};
MXD_U8 regVal;
MXD_U8 pnType;
MXD_U8 qamType;
MXD_RTN_CODE_E eRtnCode = MXD_RTN_OK;
PDEVICE_PROPERTY_S psDeviceProperty;
psDeviceProperty = (PDEVICE_PROPERTY_S)hDevice;
/*
* flush HIC buffer and clear data interrupt
*/
DDS_WriteReg( hDevice, DTMB_HIC_FLUSH_RELOAD_REG, 0x01 );
DDS_WriteReg( hDevice, DTMB_HIC_INT_CLEAR_REG, 0x07 );
DDS_WriteReg( hDevice, DTMB_HIC_PID_CONTROL_REG, 0x0);
DDS_ReadReg( hDevice, DTMB_TDP_TPS_REG, ®Val );
regVal &= 0x0f;
DDS_WriteReg( hDevice, DTMB_FDP_QAM_BSL_REG, qamBSL[regVal] );
/* config system info related register */
DDS_WriteReg( hDevice, DTMB_TDP_SYS_INFO_CFG_REG, tpsId );
qamType = (tpsId>>3)&0x07;
/* set max iter number according to QAM type */
switch(psDeviceProperty->m_PnType)
{
case 0:
case 1:
pnType = 0;
break;
case 2:
case 3:
pnType = 1;
break;
case 4:
pnType =2;
break;
default:
eRtnCode = MXD_RTN_FAIL;
break;
}
DDS_WriteReg( hDevice, DTMB_FEC_ITER_MAX_NUM_REG, (MXD_U8)(iterNum[pnType][qamType]-1) );
/* disable system info de-mapping and enable data path */
if( DEV_MODE_DTMB_SC == psDeviceProperty->m_eDevMode )
{
DDS_WriteReg( hDevice, DTMB_FDP_FDI_WORK_MODE_REG, 0x05 );
}
else
{
DDS_WriteReg( hDevice, DTMB_FDP_FDI_WORK_MODE_REG, 0x04 );
}
return eRtnCode;
}/* end of DTMB_StartStream( ) */
/*!
* Stop DTMB data reception.
*
* \param hDevice: [in] Device handle
*
* \return Return code by MXD_RTN_CODE_E enumeration.
*
* \remark null
*
*/
MXD_RTN_CODE_E MXD_API DTMB_StopStream( IN HMXDDEV hDevice )
{
MXD_RTN_CODE_E eRtnCode = MXD_RTN_OK;
/* Disable the whole chip DTMB data path */
DDS_WriteReg( hDevice, DTMB_FDP_FDI_WORK_MODE_REG, 0x0 );
DDS_WriteReg( hDevice, DTMB_HIC_PID_CONTROL_REG, 0x2);
DDS_WriteReg( hDevice, DTMB_RESET_ALL_REG, 0x00 );
OAL_Sleep(1);
DDS_WriteReg( hDevice, DTMB_RESET_ALL_REG, 0xff );
/* Flush the on-chip HIC data buffer */
DDS_WriteReg( hDevice, DTMB_HIC_FLUSH_RELOAD_REG, 0x01 );
return eRtnCode;
}/* end of DTMB_StopStream( ) */
/*!
* Query the SNR of DTMB signal.
*
* \param hDevice: [in] Device handle
*
* \return SNR value.
*
* \remark null
*
*/
MXD_U32 MXD_API DTMB_GetSnr( IN HMXDDEV hDevice )
{
MXD_U8 i;
MXD_U8 regVal = 0;
MXD_U8 stepVal = 0;
MXD_U8 agcVal = 0;
MXD_U32 agcSum = 0;
MXD_S8 snrVal;
MXD_U8 iterNum = 0;
MXD_U8 iterRefNum[16] = {30,15,30,30,
30,30,30,15,
15,10,10,10,
10,8,8,8};
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