📄 mxd_sdk_data.h
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/*!
*System Version information
*/
typedef struct _SYS_VERSION_INFO_S
{
MXD_U16 m_DeviceId; /*!<Device version ID*/
MXD_U16 m_DriverId; /*!<SDK driver CVS release tag version*/
} SYS_VERSION_INFO_S, *PSYS_VERSION_INFO_S;
/*!
*I2C property information
*/
typedef struct _I2C_PROPERTY_S
{
MXD_U16 m_DemodSlaveAddr; /*!<Demodulator slave address.*/
MXD_U16 m_BitRateKHz; /*!<I2C bitrate */
PIL_I2CREAD m_pPIL_I2cRead; /*!<I2C Read*/
PIL_I2CWRITE m_pPIL_I2cWrite; /*!<I2C Write*/
} I2C_PROPERTY_S, *PI2C_PROPERTY_S;
/*!
*MP2TS property information
*/
typedef struct _MP2TS_PROPERTY_S
{
MXD_U8 m_DataMode; /*!<Parallel or Serial Data*/
MXD_U8 m_ByteMode; /*!<MSB or LSB first.*/
MXD_U8 m_TriggerEdge;/*!<Positive or Negative trigger edge.*/
MXD_U8 m_Reserved; /*!<For 32bit order. */
MXD_U32 m_SpeedKHz; /*!<MP2TS speed in KHz*/
} MP2TS_PROPERTY_S, *PMP2TS_PROPERTY_S;
/*!
* SPI Property Information
*/
typedef struct _SPI_PROPERTY_S
{
MXD_U8 m_CsIdx; /*!<CS pin index*/
MXD_U8 m_Reserved; /*!<For 32bit order. */
MXD_U16 m_BitRateKHz; /*!<SPI speed.*/
PMXD_U8 m_pDevTxBuffer; /*!<SPI TX Temp buffer*/
PMXD_U8 m_pDevRxBuffer; /*!<SPI RX Temp buffer*/
MXD_U32 m_ByteLen; /*!<SPI bulk read length */
SPI_WORK_MODE_E m_SpiMode; /*!<0: moto mode 0;1: moto mode 1;2: moto mode 2;3: moto mode 3;4 TI mode (3-wire);*/
PIL_SPITRX m_pPIL_SpiTrx; /*!<SPI Tx/Rx */
} SPI_PROPERTY_S, *PSPI_PROPERTY_S;
/*!
* SDIO Property Information
*/
typedef struct _SDIO_PROPERTY_S
{
MXD_U32 m_Reserved; /*!<Reserved*/
} SDIO_PROPERTY_S, *PSDIO_PROPERTY_S;
/*!
* SDRAM Property Information
*/
typedef struct _SDRAM_PROPERTY_S
{
MXD_U8 m_Cas; /*!<CAS*/
MXD_U8 m_BurstType; /*!<Burst type*/
MXD_U8 m_BurstLength; /*!<Burst length*/
MXD_U8 m_RefreshPeriod; /*!<Refresh Period*/
MXD_U8 m_Rfc;/*auto refresh duration*/
MXD_U8 m_Rrd;/*active to active interval cycles in the same bank*/
MXD_U8 m_Rc;/*active to active interval cycles for different bank*/
MXD_U8 m_Ras;/*active to precharge interval cycles*/
MXD_U8 m_Rp;/*prechareg duration cycles*/
MXD_U8 m_Mrd;/*!<sdram mode register set duration*/
MXD_U8 m_Xp; /*!<sdram power down exit to any valid commond interval. */
MXD_U8 m_Twr; /*!<sdram write recovery cycles. */
MXD_U32 m_CalibVal;/*!< sdram calibration value.*/
} SDRAM_PROPERTY_S, *PSDRAM_PROPERTY_S;
/*!
* Demodulator Channel Property Information
*/
typedef struct _CHANNEL_PROPERTY_S
{
MXD_IF_TYPE_E m_eRegAccessType; /*!<Register access interface type: i2c/spi/sdio*/
MXD_IF_TYPE_E m_eTsStreamAccessType; /*!<TS stream access interface: mp2ts/spi/sdio*/
MXD_IF_TYPE_E m_eDataAccessType; /*!<Data access interface: spi/sdio*/
HMXDDEV m_hI2c; /*!<I2c master device handle*/
HMXDDEV m_hMp2ts; /*!<Mp2ts slave device handle.*/
HMXDDEV m_hSpi; /*!<SPI master device handle*/
HMXDDEV m_hSdio; /*!<SDIO master device handle*/
} CHANNEL_PROPERTY_S, *PCHANNEL_PROPERTY_S;
/*!
* Callback Setting Information
*/
typedef struct _CALLBACK_SETTING_S
{
MXD_U32 m_DtmbDataThrd; /*!<The threshold for data interrupt in DTMB mode. */
MXD_U32 m_DmbSch1Thrd; /*!<The threshold for sub-channel 1 in DMB mode. 20*188 is recommended.*/
MXD_U32 m_DmbSch2Thrd; /*!<The threshold for sub-channel 2 in DMB mode. 20*188 is recommended.*/
PIL_DATAINTCALLBACK m_pPIL_DataIntCallback; /*!<Data interrupt callback for current platform.*/
PIL_SYNCINTCALLBACK m_pPIL_StatusIntCallback; /*!<Sync interrupt callback for current platform.*/
PIL_UNLOCKCALLBACK m_pPIL_UnlockCallback;/*!<Unlock Callback for current platform.*/
} CALLBACK_SETTING_S, *PCALLBACK_SETTING_S;
/*!
* Demodulator Property Information
*/
typedef struct _DEMOD_PROPERTY_S
{
MXD_U8 m_IntMode; /*!0:Level mode(default) 1:Edge mode */
MXD_U8 m_IntLevel; /*! 0: low level in level mode, falling edge in edge mode. 1:high level int level mode, rising edge in edge mode.*/
MXD_U8 m_IntType; /*! 0: interrupt using spi/sdio mac protocol: interrupt not using spi/sdio mac protocol */
MXD_U8 m_TpsStatus; /*! tps status */
MXD_U8 m_EepromAddr; /*! Eeprom slave address */
MXD_U16 m_MtxLoadLen; /*! 2^n; n<=9*/
CALLBACK_SETTING_S m_sCbSetting; /*!<Callback communication setting*/
CHANNEL_PROPERTY_S m_sChannelProperty; /*!<Demodulator channel property*/
I2C_PROPERTY_S m_sI2cProperty; /*!<I2C property*/
MP2TS_PROPERTY_S m_sMp2tsProperty; /*!<MP2TS property*/
SPI_PROPERTY_S m_sSpiProperty; /*!<SPI property*/
SDIO_PROPERTY_S m_sSdioProperty; /*!<SDIO property*/
SDRAM_PROPERTY_S m_sSdramProperty; /*!<SDRAM property*/
} DEMOD_PROPERTY_S, *PDEMOD_PROPERTY_S;
/*!
* Tuner Property Information
*/
typedef struct _TUNER_PROPERTY_S
{
MXD_U8 m_SlaveAddr; /*!<Tuner slave address.*/
MXD_U8 m_LifOrNZif; /*!<0: ZIF; 1: LIF*/
MXD_U8 m_IfRate; /*!<2:2X; 4:4X; 6: 6X*/
MXD_U8 m_Reserved; /*!<reserved */
MXD_S32 m_LifFreqKhz; /*!<LIF frequency.*/
MXD_U32 m_FreqOffset; /*!< frequency offset .*/
PIL_INITTUNER m_pPIL_InitTuner; /*!<Init for tuner (including TIU and tuner itself)*/
PIL_SETFREQ m_pPIL_SetFreq; /*!<Tune frequency*/
PIL_GETTUNERSTATUS m_pPIL_GetTunerStatus; /*!<Get tuner status*/
} TUNER_PROPERTY_S, *PTUNER_PROPERTY_S;
/*!
* DTMB system information
*/
typedef struct _DTMB_SYSTEM_INFO_S
{
MXD_U8 m_QamType; /*!<QAM Type: Type 1: 4QAM, Type 2: 16QAM, Type 3: 32QAM, Type 4: 64QAM, Type 5: 4QAM-NR*/
MXD_U8 m_LdpcCodeRateType; /*!<LDPC Code Rate Type: Type 1: 0.4, Type 2: 0.6, Type 3: 0.8*/
MXD_U8 m_InterleaveType; /*!<Interleave Type:Type 1: Interleave Width(B = 52), Interleave Depth(M = 240), Type 2: Interleave Width(B = 52), Interleave Depth(M = 720)*/
MXD_U8 m_Reserved; /*!<Reserved*/
} DTMB_SYSTEM_INFO_S, *PDTMB_SYSTEM_INFO_S;
/*!
* Device Property Information
*/
typedef struct _DEVICE_PROPERTY_S
{
HMXDDEV m_hDevice; /*!<Device handle.*/
DEVICE_WORK_MODE_E m_eDevMode; /*!<Device work mode*/
MXD_U8 m_PnType; /*!<PN type: 0x00: 420 fix; 0x01: 420 rotation; 0x02: 945 fix; 0x03: 945 rotation; 0x04: 595;*/
MXD_U8 m_Reserved1; /*!<Reserved*/
MXD_U16 m_Reserved2; /*!<Reserved*/
MXD_U32 m_FreqHz; /*!<Frequency in Hz*/
MXD_U32 m_InitFo; /*!<Init fo value*/
MXD_U32 m_DU; /*!<DU */
DEMOD_PROPERTY_S m_sDemod; /*!<Demodulator property*/
TUNER_PROPERTY_S m_sTuner; /*!<Tuner property*/
MXD_RTN_CODE_E m_LastErrStatus; /* return status for no MXD_RTN_CODE_E function */
} DEVICE_PROPERTY_S, *PDEVICE_PROPERTY_S;
/*!
* DTMB service map information.
*/
typedef struct _DTMB_SERVICE_MAP_S
{
MXD_U32 m_FreqHz; /*!<Frequency in Hz.*/
MXD_U16 m_McOrSc; /*!<1: Multi-carrier; 0: Single-carrier*/
MXD_U8 m_PnType; /*!<PN type: 0x00: 420 fix; 0x01: 420 rotation; 0x02: 945 fix; 0x03: 945 rotation; 0x04: 595;*/
MXD_U8 m_TpsId; /*!<TPS value to be configured.*/
MXD_U32 m_Reserved; /*!<Reserved*/
DTMB_SYSTEM_INFO_S m_sDtmbSysInfo; /*!<System information for current service*/
} DTMB_SERVICE_MAP_S, *PDTMB_SERVICE_MAP_S;
#ifdef WIN32
#pragma pack(pop)
#endif
/**********************************************************************************
*
* Device Config Definitions
*
**********************************************************************************
*/
/*!
* Device Config API Typedef
*/
typedef void (MXD_API *PIL_DEVICECONFIG)(
IN PDEMOD_PROPERTY_S pDemodProperty,
IN PTUNER_PROPERTY_S pTunerProperty);
/**********************************************************************************
*
* Register Definitions
*
**********************************************************************************
*/
/* regs of chip interrupt module */
#define DTMB_HIC_INT_STATUS_REG 0x00
#define DTMB_HIC_INT_CLEAR_REG 0x01
#define DTMB_HIC_INT_MASK_REG 0x02
#define DTMB_TDP_INT_STATUS_REG 0x03
#define DTMB_TDP_INT_CLEAR_REG 0x04
#define DTMB_TDP_INT_MASK_REG 0x05
#define DTMB_RESET_ALL_REG 0x14
#define DTMB_FDP_UFO_IDX_H_REG 0x1E
#define DTMB_FDP_UFO_IDX_L_REG 0x1F
#define DTMB_STATUS_SEM_REG 0x20
/* regs of chip TDP module */
#define DTMB_MISC_READ_FREEZE_REG 0x25
#define DTMB_TDP_TRK_PRE_NUM_REG 0x26
#define DTMB_TDP_PWM_THD_REG 0x27
#define DTMB_TDP_TIME_DELAY_REG 0x28
#define DTMB_TDP_BSL_REG 0x29
#define DTMB_TDP_IF_TYPE_REG 0x2A
#define DTMB_TDP_CTS_THD_REG 0x2B
#define DTMB_TDP_INIT_FO_H_REG 0x2C
#define DTMB_TDP_INIT_FO_M_REG 0x2D
#define DTMB_TDP_INIT_FO_L_REG 0x2E
#define DTMB_TDP_DU_H_REG 0x2F
#define DTMB_TDP_DU_M_REG 0x30
#define DTMB_TDP_DU_L_REG 0x31
#define DTMB_TDP_RTO_INT_REG 0x32
#define DTMB_TDP_RTO_FRT_H_REG 0x33
#define DTMB_TDP_RTO_FRT_M_REG 0x34
#define DTMB_TDP_RTO_FRT_L_REG 0x35
#define DTMB_TDP_INIT_REG 0x36
#define DTMB_TDP_WORK_MODE_REG 0x37
#define DTMB_TDP_FID_PARA_REG 0x38
#define DTMB_TDP_OFO_LENGTH_REG 0x39
#define DTMB_TDP_FID_RESULT_REG 0x3A
#define DTMB_TDP_SYS_INFO_CFG_REG 0x3B
#define DTMB_TDP_Q_SCALE_REG 0x3E
#define DTMB_TDP_ZSP_PARA_REG 0x3F
#define DTMB_TDP_FO_MS_REG 0x40
#define DTMB_TDP_OFO_VALUE_H_REG 0x41
#define DTMB_TDP_OFO_VALUE_L_REG 0x42
#define DTMB_TDP_FPP_H_REG 0x43
#define DTMB_TDP_FPP_M_REG 0x44
#define DTMB_TDP_FPP_L_REG 0x45
#define DTMB_TDP_ZSP_H_REG 0x46
#define DTMB_TDP_ZSP_M_REG 0x47
#define DTMB_TDP_ZSP_L_REG 0x48
#define DTMB_TDP_AFLT_TYPE_REG 0x49
#define DTMB_TDP_AGC_OFFSET_REG 0x4A
#define DTMB_TDP_CPE_RESULT_REG 0x4B
#define DTMB_TDP_RSSI_REG 0x4C
#define DTMB_TDP_FTT_PARA_REG 0x4D
#define DTMB_TDP_FTT_THD_REG 0x4E
#define DTMB_TDP_PNUM_REG 0x4F
#define DTMB_TDP_SET_ZERO_RANGE_REG 0x50
#define DTMB_TDP_FTT_MIN_THD_REG 0x51
#define DTMB_CPE_PARA_REG 0x52
#define DTMB_CPE_THD_REG 0x53
#define DTMB_TDP_AGC_PARA_REG 0x54
#define DTMB_TDP_TPS_REG 0x55
#define DTMB_TDP_CTS_RESULT_L_REG 0x56
#define DTMB_TDP_CTS_RESULT_H_REG 0x57
#define DTMB_TDP_FTT_MAX_FG_L_REG 0x58
#define DTMB_TDP_FTT_MAX_FG_H_REG 0x59
#define DTMB_TDP_ZSP_MS_REG 0x5A
#define DTMB_TDP_ZSP_IS_REG 0x5B
#define DTMB_TDP_PWM_INI_REG 0x5C
#define DTMB_TDP_IQREF_REG 0x5D
#define DTMB_TDP_PWM_CONTROL_REG 0x5E
#define DTMB_TDP_PWM_CLK_STEP_REG 0x5F
#define DTMB_TDP_TPS_SUM_I_REG 0x60
#define DTMB_TDP_TPS_SUM_Q_REG 0x61
#define DTMB_TDP_RFO_RESULT_REG 0xE6
#define DTMB_TDP_NOISE_IQ_REG 0xE7
#define DTMB_TDP_PWM_UPPER_BOUND_REG 0xE8
#define DTMB_TDP_PWM_LOWER_BOUND_REG 0xE9
#define DTMB_TDP_HOLD_AGC_TIME_REG 0xEA
#define DTMB_TDP_FTT_FAIL_CNT_REG 0xEB
#define DTMB_TDP_CYPT_STEP_H_REG 0xEC
#define DTMB_TDP_CYPT_STEP_L_REG 0xED
#define DTMB_TDP_AGC_AFLT_PARA_REG 0xEE
#define DTMB_TDP_CTS_RS_INISTEP_REG 0xEF
#define DTMB_TDP_CTS_RS_CONFIG_REG 0xF0
#define DTMB_TDP_NOISE_IQ_MAX_H_REG 0xF1
#define DTMB_TDP_NOISE_IQ_MAX_L_REG 0xF2
/* regs of chip FDP module */
#define DTMB_FDP_FDI_WORK_MODE_REG 0x62
#define DTMB_FDP_ABC_OFFSET_REG 0x64
#define DTMB_FDP_QAM_BSL_REG 0x66
#define DTMB_FDP_CARRIER_MODE_REG 0x67
#define DTMB_FDP_SCALE_REG 0x68
#define DTMB_FDP_SC_DP_BSL_REG 0x69
#define DTMB_FDP_MUL_BSL_REG 0x6A
#define DTMB_FDP_SDIV_BSL_REG 0x6B
#define DTMB_FDP_MC_BSL_REG 0x6C
#define DTMB_FDP_HW_DIV_THD_REG 0x6D
/* regs of chip SDI module */
#define DTMB_SDI_BYPASS_EN_REG 0x6E
#define DTMB_SDI_SDRM_START_ADDR_H_REG 0x6F
#define DTMB_SDI_SDRM_START_ADDR_L_REG 0x70
/* regs of chip FEC module */
#define DTMB_FEC_CONFIG_REG 0x71
#define DTMB_FEC_ITER_MAX_NUM_REG 0x72
#define DTMB_FEC_ITER_REAL_NUM_REG 0x73
#define DTMB_FEC_BER_HH_REG 0x74
#define DTMB_FEC_BER_H_REG 0x75
#define DTMB_FEC_BER_M_REG 0x76
#define DTMB_FEC_BER_L_REG 0x77
#define DTMB_FEC_BLER_H_REG 0x78
#define DTMB_FEC_BLER_L_REG 0x79
#define DTMB_SDRM_MR_H_REG 0x7D
#define DTMB_SDRM_MR_L_REG 0x7E
#define DTMB_SDRM_REFRESH_TIMING_REG 0x81
#define DTMB_SDRM_ACTIVE_TIMING_REG 0x82
#define DTMB_SDRM_PRECHARGE_TIMING_REG 0x83
#define DTMB_SDRM_MISC_TIMING_REG 0x84
#define DTMB_SDRM_MISC_CTRL_REG 0x85
#define DTMB_SDRM_PD_CNT_REG 0x86
#define DTMB_SDRM_CALI_CONTROL_REG 0x87
#define DTMB_SDRM_INIT_BGN_REG 0x88
#define DTMB_SDRM_INIT_CMD_H_REG 0x89
#define DTMB_SDRM_INIT_CMD_M_REG 0x8A
#define DTMB_SDRM_INIT_CMD_L_REG 0x8B
#define DTMB_SDRM_INIT_CONTROL_REG 0x8D
#define DTMB_SDRM_INIT_RDY_REG 0x8E
#define DTMB_HIC_PID_IDX_REG 0x8F
#define DTMB_HIC_PID_WR_VAL_H_REG 0x90
#define DTMB_HIC_PID_WR_VAL_L_REG 0x91
#define DTMB_HIC_PID_RD_VAL_H_REG 0x92
#define DTMB_HIC_PID_RD_VAL_L_REG 0x93
#define DTMB_HIC_PID_OP_REG 0xB1
/* regs of chip HIC module */
#define DTMB_HIC_FLUSH_RELOAD_REG 0x94
#define DTMB_HIC_PID_CONTROL_REG 0x95
#define DTMB_HIC_SDRM_ROW_BADDR_H_REG 0x96
#define DTMB_HIC_SDRM_ROW_BADDR_L_REG 0x97
#define DTMB_HIC_SDRM_ROW_EADDR_H_REG 0x98
#define DTMB_HIC_SDRM_ROW_EADDR_L_REG 0x99
#define DTMB_HIC_MTX_ROW_EADDR_H_REG 0x9A
#define DTMB_HIC_MTX_ROW_EADDR_L_REG 0x9B
#define DTMB_HIC_MTX_SEL_REG 0x9C
#define DTMB_HIC_DATA_THLD_H_REG 0x9D
#define DTMB_HIC_DATA_THLD_M_REG 0x9E
#define DTMB_HIC_DATA_THLD_L_REG 0x9F
#define DTMB_HIC_DATA_AVAIL_CNT_H_REG 0xA0
#define DTMB_HIC_DATA_AVAIL_CNT_M_REG 0xA1
#define DTMB_HIC_DATA_AVAIL_CNT_L_REG 0xA2
#define DTMB_HIC_SDRM_DIR_ADDR_H_REG 0xA3
#define DTMB_HIC_SDRM_DIR_ADDR_M_REG 0xA4
#define DTMB_HIC_SDRM_DIR_ADDR_L_REG 0xA5
#define DTMB_HIC_SDRM_DIR_ENABLE_REG 0xA6
#define DTMB_HIC_SDRM_DIR_ACCESS_REG 0xA7
#define DTMB_HIC_SDRM_DIR_WR_DATA_H_REG 0xA8
#define DTMB_HIC_SDRM_DIR_WR_DATA_L_REG 0xA9
#define DTMB_HIC_SDRM_DIR_RD_DATA_H_REG 0xAA
#define DTMB_HIC_SDRM_DIR_RD_DATA_L_REG 0xAB
#define DTMB_FEC_CONTI_ERRNUM_DIS_THD_REG 0xAC
#define DTMB_FEC_TOTAL_ERRNUM_DIS_THD_REG 0xAD
#define DTMB_FEC_TOTAL_ERRNUM_RES_THD_L_REG 0xAE
#define DTMB_FEC_TOTAL_ERRNUM_RES_THD_H_REG 0xAF
#define DTMB_FEC_DISCARD_CONFIG_REG 0xB0
/* regs of HIC module */
#define COMMON_HIC_INT_CTRL_REG 0xB4
#define COMMON_CIR_SDRM_IO_CTRL_REG 0xB5
#define COMMON_HIC_IO_TYPE_REG 0xB6
#define COMMON_ADC_MODE_CTRL_REG 0xB7
#define COMMON_HIC_I2C_BLOCK_LENGTH_REG 0xB8
#define COMMON_HIC_SPI_CTRL_REG 0xB9
#define COMMON_HIC_MP2TS_CONFIG_REG 0xBA
#define COMMON_ADC_TEST_PINS_REG 0xBB
#define COMMON_TOP_HARD_MODE_SEL_PINS_REG 0xBC
#define COMMON_EXTERNAL_CLK_GATE_EN_REG 0xBD
#define COMMON_VERSION_REG 0xBE
#define COMMON_DMB_MODE_SEL_REG 0xBF
/* regs of Tuner interface controll */
#define COMMON_TIC_CONTROL_REG 0xC0
#define COMMON_TIC_TUNER_SLAVE_ADDR_REG 0xC1
#define COMMON_TIC_I2C_BIT_RATE_REG 0xC2
#define COMMON_TIC_STATUS_REG 0xC3
#define COMMON_TIC_HOST_ACCESS_BYTE_NUM_REG 0xC4
#define COMMON_TIC_TUNER_WRDATA_D_REG 0xC5
#define COMMON_TIC_TUNER_WRDATA_C_REG 0xC6
#define COMMON_TIC_TUNER_WRDATA_B_REG 0xC7
#define COMMON_TIC_TUNER_WRDATA_A_REG 0xC8
#define COMMON_TIC_TUNER_WRADDR_REG 0xC9
#define COMMON_TIC_TUNER_RDADDR_REG 0xCA
#define COMMON_TIC_TUNER_RDDATA_D_REG 0xCB
#define COMMON_TIC_TUNER_RDDATA_C_REG 0xCC
#define COMMON_TIC_TUNER_RDDATA_B_REG 0xCD
#define COMMON_TIC_TUNER_RDDATA_A_REG 0xCE
#define COMMON_TIC_TUNER_AGC_ADDR_REG 0xD0
#define COMMON_TIC_AGC_MASK_H_REG 0xD1
#define COMMON_TIC_AGC_MASK_M_REG 0xD2
#define COMMON_TIC_AGC_MASK_L_REG 0xD3
#define COMMON_TIC_AGC_LUT_WRDATA_H_REG 0xD4
#define COMMON_TIC_AGC_LUT_WRDATA_M_REG 0xD5
#define COMMON_TIC_AGC_LUT_WRDATA_L_REG 0xD6
#define COMMON_TIC_AGC_LUT_WRADDR_H_REG 0xD7
#define COMMON_TIC_AGC_LUT_WRADDR_L_REG 0xD8
#define COMMON_TIC_AGC_LUT_RDADDR_H_REG 0xD9
#define COMMON_TIC_AGC_LUT_RDADDR_L_REG 0xDA
#define COMMON_TIC_AGC_LUT_RDDATA_H_REG 0xDB
#define COMMON_TIC_AGC_LUT_RDDATA_M_REG 0xDC
#define COMMON_TIC_AGC_LUT_RDDATA_L_REG 0xDD
#define COMMON_TIC_SLAVE_HIGH_ADDR_REG 0xDE
#define COMMON_TIC_MTX_ROW_NUM_REG 0xDF
#define COMMON_TIC_EEPROM_BOOT_ENABLE_REG 0xE5
/* end of register definitions */
#ifdef __cplusplus
}
#endif
#endif/* __MXD_SDK_DATA_H__ */
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