altera.tab

对于研究FPGA结构的人来说

.DEFINE AND4(IN1,IN2,IN3, IN4; Y)
1111 1
.MAP AND3 AND4(IN1, IN2, IN3, 1; Y)
.MAP AND2 AND3(IN1, IN2, 1; Y)
.MAP AND1 AND2(IN1, 1; Y)
.ALIAS DELAY AND1

.LATCH FF(D, CLK; Q)
.LATCH DFF(D, CLK, !CLRN, !PRN; Q)
.LATCH DFFE(D, CLK, !CLRN, !PRN, !ENA; Q)

.DEFINE INV(IN1; Y)
0 1

.ALIAS FILTER AND1

.DEFINE OR8(IN1, IN2, IN3, IN4, IN5, IN6, IN7, IN8; Y)
1------- 1
-1------ 1
--1----- 1
---1---- 1
----1--- 1
-----1-- 1
------1- 1
-------1 1
.MAP OR7 OR8(IN1, IN2, IN3, IN4, IN5, IN6, IN7, 0; Y)
.MAP OR6 OR7(IN1, IN2, IN3, IN4, IN5, IN6, 0; Y)
.MAP OR5 OR6(IN1, IN2, IN3, IN4, IN5, 0; Y)
.MAP OR4 OR5(IN1, IN2, IN3, IN4, 0; Y)
.MAP OR3 OR4(IN1, IN2, IN3, 0; Y)
.MAP OR2 OR3(IN1, IN2, 0; Y)

.ALIAS OR1 AND1

.DEFINE TRIBUF(IN1, !OE; Y)
1 1

.DEFINE XOR2(IN1, IN2; Y)
10 1
01 1

.END