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📄 e_table.c

📁 对于研究FPGA结构的人来说
💻 C
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			pCell->pViewLL->nIn++;			pCell->pViewLL->ports[i].ignore = 0;		}		pCell->pViewLL->ports[i].pNet = NULL;	}	for(i++; i<nOut+nIn; i++) {		pCell->pViewLL->ports[i].name = _strip_space(strtok(NULL, ","));		pCell->pViewLL->ports[i].direction = in;		if(pCell->pViewLL->ports[i].name[0]=='!') {			strcpy(pCell->pViewLL->ports[i].name, pCell->pViewLL->ports[i].name+1);			pCell->pViewLL->ports[i].ignore = 1;		} else {			pCell->pViewLL->nIn++;			pCell->pViewLL->ports[i].ignore = 0;		}		pCell->pViewLL->ports[i].pNet = NULL;	}		pCell->pViewLL->nOutPorts = nOut;	pCell->pViewLL->nPorts = nOut+nIn;	pCell->pViewLL->pFirstInstance = NULL;	pCell->pViewLL->pFirstNet = NULL;	pCell->pViewLL->TT = NULL;	*targetCell = pCell;	return 0;}intread_table(char *filename, LIBRARY *lib){	FILE *fp;	int c;	char buffer[4097];		my_assert(lib && filename);	fp = fopen(filename, "rt");	if(!fp) {		error("Error opening file '%s' for reading.\n");		return -1;	}		info("\n** Reading Translation Table '%s' **\n", filename);	for(;;) {		c = fgetc(fp);		if(c==EOF) {			error("Error: Premature end-of-file. File must end with '.end'\n");			return -1;		} else if(c=='#') {			fgets(buffer, 4096, fp);			continue;		} else if(isspace(c)) {			continue;		} else if(c!='.') {			error("Error: Unexpected character '%c' found.\n", c);			return -1;		}		fscanf(fp, "%s", buffer);		if(!strcasecmp(buffer, "DEFINE")) {			CELL *pCell, *pTemp;			int nIn, i;			if(_read_cell(fp, &pCell))				return -1;			if(pCell->pViewLL->nOutPorts>1) {				error("Error: Logic entities with more than one output currently not supported.\n");				return -1;			}			if(pCell->pViewLL->nPorts>31) {				error("Error: Logic entities with more than 30 inputs not supported.\n");				return -1;			}			nIn = pCell->pViewLL->nIn;			i = (nIn >= 3) ? (1<<(nIn-3)) : 1;			pCell->pViewLL->TT = (char *) malloc(i * sizeof(char));			mem_assert(pCell->pViewLL->TT);			memset(pCell->pViewLL->TT, 0, i);			/* Read in the truth table */			for(;;) {				c = fgetc(fp);				if(c==EOF) {					error("Error: Unexpected EOF.\n");					return -1;				} else if(c=='.' || c=='#') {					ungetc(c, fp);					break;				} else if(isspace(c)) {					continue;				} else if(c=='0' || c=='1' || c=='-') {					int byte, bit;					char ch;					/* Check special case of nIn=0 */					if(nIn==0) {						if(c=='-') {							error("Error: Constant generators may only contain"								" 1 or 0 in define '%s'", pCell->name);							return -1;						}						pCell->pViewLL->TT[0] = c-'0';						continue;					}					ungetc(c, fp);					fscanf(fp, "%s %c", buffer, &ch);					if(ch != '1') {						error("Error: Truth table format incorrect for "							"define '%s'.  \n\tPossibility: value must be a "							"'1' not a '%c'.\n", pCell->name, ch);						return -1;					}					if(strlen(buffer)!=nIn) {						error("Error: Truth table row doesn't have enough"							" entries in define '%s'.\n", pCell->name);						return -1;					}					if(_fill_TT(buffer, nIn, pCell->pViewLL->TT, 0, 0)) {						error("Error: Bad character found in TT for define"							" '%s'.\n", pCell->name);						return -1;					}					continue;				}				error("Error: Unexpected character '%c' in define '%s'\n", c, pCell->name);				return -1;			}				if(_add_cell(pCell, lib))				return -1;			verbose("\nDEFINE ");			_print_cell(pCell);		} else if(!strcasecmp(buffer, "ALIAS")) {			CELL *pCell, *pCell2;			fscanf(fp, "%s", buffer);			pCell = (CELL *) malloc(sizeof(CELL));			mem_assert(pCell);						pCell->name = strdup(buffer);						fscanf(fp, "%s", buffer);			pCell2 = hash_get(lib->pCellHT, buffer);			if(!pCell2) {				error("Error: Attempt to alias '%s' onto non-existant "					"cell '%s'\n", pCell->name, buffer);				return -1;			}			pCell->pViewLL = (NETLISTVIEW *) malloc(sizeof(NETLISTVIEW));			mem_assert(pCell->pViewLL);			pCell->pViewLL->ports = NULL;			pCell->pViewLL->tag = pCell2->pViewLL->tag;			pCell->pViewLL->name = NULL;			pCell->pViewLL->nOutPorts = pCell2->pViewLL->nOutPorts;			pCell->pViewLL->nPorts = pCell2->pViewLL->nPorts;			pCell->pViewLL->nIn = pCell2->pViewLL->nIn;			pCell->pViewLL->pFirstInstance = NULL;			pCell->pViewLL->pFirstNet = NULL;			if(pCell->pViewLL->tag == logic) {				pCell->pViewLL->TT = (char *) malloc(sizeof(char) * (1<<(pCell2->pViewLL->nIn)));					mem_assert(pCell->pViewLL->TT);				memcpy(pCell->pViewLL->TT, pCell2->pViewLL->TT, sizeof(char) * ((pCell2->pViewLL->nIn) > 3) ? (1 << (pCell2->pViewLL->nIn-3)) : 1);			} else if(pCell->pViewLL->tag == latch) {				pCell->pViewLL->input_pin = pCell2->pViewLL->input_pin;				pCell->pViewLL->clock_pin = pCell2->pViewLL->clock_pin;				pCell->pViewLL->output_pin = pCell2->pViewLL->output_pin;							} else {				my_assert(0);			}			if(_add_cell(pCell, lib))				return -1;			verbose("\nALIAS ");			_print_cell(pCell);  		} else if(!strcasecmp(buffer, "MAP")) {			CELL *pCell, *tCell, *pTemp;			int count=0, nIn, nTT, sizeTT, pos, i;			fscanf(fp, "%s", buffer);			if(_read_cell(fp, &tCell))				return -1;						pCell = (CELL *) hash_get(lib->pCellHT, tCell->name);			if(!pCell) {				error("Error: Attempt to map cell '%s' onto non-existant "					"cell '%s'.\n", buffer, tCell->name);				return -1;			} else if((pCell->pViewLL->nPorts!=tCell->pViewLL->nPorts) || (pCell->pViewLL->nOutPorts!=tCell->pViewLL->nOutPorts)) {				error("Error: Attempt to map cell '%s' onto cell '%s', but sizes do not match.\n", buffer, tCell->name);				return -1;			}						free(tCell->name);			tCell->name = strdup(buffer);			nIn = pCell->pViewLL->nIn;			nTT = 1<<nIn;			sizeTT = (nIn >= 3) ? (1<<(nIn-3)) : 1;			tCell->pViewLL->TT = (char *) malloc(sizeTT * sizeof(char));			mem_assert(tCell->pViewLL->TT);			memcpy(tCell->pViewLL->TT, pCell->pViewLL->TT, sizeTT);			pos = 0;			for(i=tCell->pViewLL->nOutPorts; i<tCell->pViewLL->nPorts; i++) {				if(!strcmp(tCell->pViewLL->ports[i].name, "1") ||				   !strcmp(tCell->pViewLL->ports[i].name, "0")) {					int j;					for(j=0; j<nTT; j++)						if((j>>(nIn-count-1))%2==tCell->pViewLL->ports[i].name[0] - '0') {							if(tCell->pViewLL->TT[j/8] & (1<<(j%8)))								tCell->pViewLL->TT[pos/8] |= 1<<(pos%8);							else								tCell->pViewLL->TT[pos/8] &= ~(1<<(pos%8));							pos++;						}					nTT = nTT >> 1;					tCell->pViewLL->nPorts--;					tCell->pViewLL->nIn--;					free(tCell->pViewLL->ports[i].name);						for(j=i; j<tCell->pViewLL->nPorts; j++) 						tCell->pViewLL->ports[j] = tCell->pViewLL->ports[j+1];					i--;					nIn--;				} else {					count++;				}			}			if(_add_cell(tCell, lib))				return -1;			verbose("\nMAP ");			_print_cell(tCell);		} else if(!strcasecmp(buffer, "LATCH")) {			CELL *pCell, *pTemp;			NETLISTVIEW *pView;			int flag, i;			if(_read_cell(fp, &pCell)) {				error("Error parsing LATCH statement.\n");				return -1;			}			pView = pCell->pViewLL;			pView->tag = latch;						/* Validate that the output pin is port 0 */			if(pView->ports[0].ignore) {				error("Error:  Latch '%s' has ignored output pin.\n", pCell->name);				return -1;			} else {				pView->output_pin = 0;			}			/* Find the input pin */			for(i=pView->nOutPorts; i<pView->nPorts; i++) {				if(!pView->ports[i].ignore) {					pView->input_pin = i;					break;				}			}			if(i>=pView->nPorts) {				error("Error: Latch '%s' has no input pin.\n", pCell->name);				return -1;			}			/* Find the clock pin (if any) */			for(i++; i<pView->nPorts; i++) {				if(!pView->ports[i].ignore) {					pView->clock_pin = i;					break;				}			}			if(i>=pView->nPorts) {				/* No clock pin */				pView->clock_pin = -1;			}			/* Ignore all other pins */			flag = 0;			for(i=0; i<pView->nPorts; i++) {				if(!pView->ports[i].ignore && i!=pView->output_pin && i!=pView->input_pin && (pView->clock_pin==-1 || i!=pView->clock_pin)) {					pView->ports[i].ignore = 1;					flag++;				}			}			if(flag) {				warn("Warning:  %d ports automatically ignored on latch '%s'\n", pCell->name);				return -1;			}			if(_add_cell(pCell, lib))				return -1;			verbose("\nLATCH ");			_print_cell(pCell);		} else if(!strcasecmp(buffer, "INCLUDE")) {			fscanf(fp, "%s", buffer);			verbose("Reading INCLUDE file %s\n", buffer);			read_table(buffer, lib);		} else if(!strcasecmp(buffer, "END")) {			fclose(fp);			return 0;		}	}}

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