sipo.vhd

Filo Serial-Input to Paralle-output

-- SIPO.vhd

-- Registro SIPO

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all; 

entity Registro_SIPO is
   generic
   (
      n: integer:= 32
   );

   port
      (
          in_s : in std_logic;  -- Entrada serie
          Clk  : in std_logic;   -- Reloj
          Ou_p : out std_logic_vector(n-1 downto 0) -- Salida paralelo
       );
   end Registro_SIPO;

architecture Desplazamiento of Registro_SIPO is
   signal Qpp, Qnn : std_logic_vector(n-1 downto 0);
   begin

      Combinacional: process(in_s, Qpp)
      begin
         for i in 0 to n-2 loop
            Qnn(i) <= Qpp(i+1);
         end loop;            
         Qnn(n-1) <= in_s;
         Ou_p <= Qpp;

      end process Combinacional;

      Secuencial : process (Clk)
         begin
            if (Clk'event and Clk='1') then
               Qpp <= Qnn;
            end if;
         end process Secuencial;
   end Desplazamiento;