📄 bsp_cfg.h.svn-base
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// File: bsp_cfg.h
//
// This file contains system constant specific for SMDK2443 board.
//
#ifndef __BSP_CFG_H
#define __BSP_CFG_H
//------------------------------------------------------------------------------
//
// Define: BSP_DEVICE_PREFIX
//
// Prefix used to generate device name for bootload/KITL
//
#define BSP_DEVICE_PREFIX "SMDK2443" // Device name prefix
//------------------------------------------------------------------------------
// Board version
//------------------------------------------------------------------------------
// If you use CPU which is EVT0 version, define only EVT0.
// We recommend newer CPU board.
// Now, you define only in smdk2443.bat file. This definition is not need.
#define EVT1 //#define EVT0
//------------------------------------------------------------------------------
// System Tick define
//------------------------------------------------------------------------------
// There are two type system ticks. choose only one type.
// Fixed tick means that tick interrupt is occurred every 1ms.
// Variable tick means that timer interrupt period is changed when power mode is in idle.
#define FIXEDTICK
//#define VARTICK
// Clock Preset value
#define PRESET_CLOCK
#define ARM_CLOCK 533
//#define ARM_CLOCK 400133
//#define ARM_CLOCK 400
//------------------------------------------------------------------------------
// Board clock
//------------------------------------------------------------------------------
#define D1_2 0x0
#define D1_4 0x1
#define D1_8 0x2
#define D1_16 0x3
#define D2 2
#define D4 4
#define D8 8
#define D16 16
//#define S3C2443_FCLK 400000000 // 399.65MHz
#ifdef PRESET_CLOCK
#if (ARM_CLOCK==533)
#define S3C2443_FCLK 534000000 // 534.00MHz
#define S3C2443_HCLK (S3C2443_FCLK/4) // divisor 4
#define S3C2443_PCLK (S3C2443_FCLK/8) // divisor 2
#define S3C2443_SCLK 96000000
#define HCLKDIV 4
#elif (ARM_CLOCK==400)
#define S3C2443_FCLK 400000000 // 534.00MHz
#define S3C2443_HCLK (S3C2443_FCLK/4) // divisor 4
#define S3C2443_PCLK (S3C2443_FCLK/8) // divisor 2
#define S3C2443_SCLK 96000000
#define HCLKDIV 4
#elif (ARM_CLOCK==400133)
#define S3C2443_FCLK 400000000 // 400.00MHz
#define S3C2443_HCLK (S3C2443_FCLK/3) // divisor 3
#define S3C2443_PCLK (S3C2443_FCLK/6) // divisor 2
#define S3C2443_SCLK 96000000
#define HCLKDIV 3
#endif
#else
#define S3C2443_BASE_REG_VA_CLOCK_POWER 0xB1000000
#define PLLVALUE (((S3C2443_CLKPWR_REG*)(S3C2443_BASE_REG_VA_CLOCK_POWER))->MPLLCON)
#define CLKDIV (((S3C2443_CLKPWR_REG*)(S3C2443_BASE_REG_VA_CLOCK_POWER))->CLKDIV0)
#define M_DIV ((PLLVALUE >> 16) & 0xff)
#define P_DIV ((PLLVALUE >> 8) & 0x3)
#define S_DIV ((PLLVALUE >> 0) & 0x1)
#define ARMDIVN ((CLKDIV >> 9) & 0xf)
#define ARMDIV (ARMDIVN == 0 ? 1 : \
(ARMDIVN == 8 ? 2 : \
(ARMDIVN == 2 ? 3 : \
(ARMDIVN == 9 ? 4 : \
(ARMDIVN == 10 ? 6 : \
(ARMDIVN == 11 ? 8 : \
(ARMDIVN == 13 ? 12 : \
(ARMDIVN == 15 ? 16 : 1) \
) \
) \
) \
) \
) \
) \
)
#define PREDIV ((CLKDIV >> 4) & 0x3)
#define HCLKDIV ((CLKDIV>>0) & 0x3)
#define PCLKDIV ((CLKDIV>>2) & 0x1)
#define HALFHCLK ((CLKDIV>>3) & 0x1)
#define S3C2443_FOUT (2 * (M_DIV + 8L) * (12000000L / (P_DIV) / (1<<S_DIV )))
#define S3C2443_FCLK (S3C2443_FOUT / ARMDIV )
#define S3C2443_HCLK (S3C2443_FOUT / (PREDIV+1) / (HCLKDIV+1)) // divisor 4
#define S3C2443_PCLK (S3C2443_HCLK / (PCLKDIV+1)) // divisor 2
#define EPLLVALUE (((S3C2443_CLKPWR_REG*)(S3C2443_BASE_REG_VA_CLOCK_POWER))->EPLLCON)
#define EPLL_M_DIV ((EPLLVALUE >> 16) & 0xff)
#define EPLL_P_DIV ((EPLLVALUE >> 8) & 0x3f)
#define EPLL_S_DIV ((EPLLVALUE >> 0) & 0x3)
#define S3C2443_SCLK ((EPLL_M_DIV + 8L) * (12000000L / (EPLL_P_DIV+2) / (1<<EPLL_S_DIV )))
#endif
#define SYS_TIMER_DIVIDER D2
#ifdef VARTICK
#define PRESCALER ((S3C2443_PCLK/(1000000*SYS_TIMER_DIVIDER)) - 1)
#define OEM_CLOCK_FREQ (S3C2443_PCLK/(PRESCALER+1)/SYS_TIMER_DIVIDER)
// Timer count for 1 ms
#define OEM_COUNT_1MS (OEM_CLOCK_FREQ / 1000) // OEM_CLOCK_FREQ = 1000000, 1000000/1000 => 1000 = 1 msec
#define RESCHED_PERIOD 1 // 10 // Reschedule period in ms
#else // FIXEDTICK
#if (S3C2443_PCLK==50000000) // For find optimized Tick count value
#define PRESCALER (9)
#else
#define PRESCALER (14)
#endif
#define TICK_PER_SEC (1000)
#define OEM_COUNT_1MS (S3C2443_PCLK/(PRESCALER+1)/SYS_TIMER_DIVIDER/TICK_PER_SEC-1)
#define RESCHED_PERIOD (1)
#endif
//------------------------------------------------------------------------------
// Debug UART1
//------------------------------------------------------------------------------
#define BSP_UART1_ULCON 0x03 // 8 bits, 1 stop, no parity
#define BSP_UART1_UCON 0x0005 // pool mode, PCLK for UART
#define BSP_UART1_UFCON 0x00 // disable FIFO
#define BSP_UART1_UMCON 0x00 // disable auto flow control
#define BSP_UART1_UBRDIV (S3C2443_PCLK/(115200*16) - 1)
//------------------------------------------------------------------------------
// Static SYSINTR Mapping for driver.
#define SYSINTR_OHCI (SYSINTR_FIRMWARE+1)
#define SYSINTR_HSMMC (SYSINTR_FIRMWARE+2)
// -----------------------------------------------------------------------------
// define For DVS, MAX1718 Preset Value
#define V800mV 800
#define V825mV 825
#define V850mV 850
#define V900mV 900
#define V925mV 925
#define V950mV 950
#define V1000mV 1000
#define V1050mV 1050
#define V1100mV 1100
#define V1150mV 1150
#define V1200mV 1200
#define V1250mV 1250
#define V1300mV 1300
#define V1350mV 1350
#define V1400mV 1400
#define V1450mV 1450
#define V1500mV 1500
#define V1550mV 1550
#define V1600mV 1600
#define V1650mV 1650
#define V1700mV 1700
#define V1750mV 1750
#define ARM_VDD 0x01
#define INT_VDD 0x02
#define ARM_INT_VDD (ARM_VDD | INT_VDD)
#ifdef DVS_EN // using EPLL LCDCLOCK, calculate idletime percentage
// 3 step Voltage level shifting HIGH<->MID<->LOW
#define UNDERSHOOT_WORKAROUND // if there is HW undershoot, define.
#define USESWPWSAVING 1
#define MVAL_USED 0
// ARM voltage corner data, 07/01/03
// MHZ min typ max
// 67 0.95 1.0 1.05
// 133 1.05 1.1 1.15
// 400 1.25 1.3 1.35
// 533 1.35 1.4 1.45
#ifdef PRESET_CLOCK
#if (ARM_CLOCK==533)
#define HIGHVOLTAGE V1300mV
#define HIGH_V_SET {V1300mV, V1100mV}
#define MIDVOLTAGE V925mV // DVS Method 4,5 use this
#define MID_V_SET {V925mV, V950mV}
#define LOWVOLTAGE V825mV // DVS Method 5 use this additionally
#define LOW_V_SET {V825mV, V850mV}
#elif (ARM_CLOCK==400133)
#define HIGHVOLTAGE V1250mV
#define HIGH_V_SET {V1250mV, V1250mV}
#define MIDVOLTAGE V1050mV // DVS Method 4,5 use this
#define MID_V_SET {V1050mV, V1050mV}
#define LOWVOLTAGE V950mV // DVS Method 5 use this additionally
#define LOW_V_SET {V950mV, V950mV}
#endif
#endif
#define VOLTAGEDELAY 16000
#define Eval_Probe 1
#define DVSON 0x1
#define HCLKHALF 0x2
#define ACTIVE 0x4
#define DeepIdle (DVSON|HCLKHALF)
#define NIdle (DVSON)
#define LazyActive (ACTIVE|DVSON|HCLKHALF)
#define SlowActive (ACTIVE|DVSON)
#define Active (ACTIVE)
#endif
//------------------------------------------------------------
#endif
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