📄 usb.c.svn-base
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Outp32(BYTE_WRITE_CNT_REG, g_uEp1MaxPktSize);
WrPktEp1(BulkInBuf, g_uEp1MaxPktSize);
g_uBulkInAddr = BaseAddr + g_uEp1MaxPktSize;
g_uBulkInCount -= g_uEp1MaxPktSize;
}
else
{
Outp32(INDEX_REG, EP1);
Outp32(BYTE_WRITE_CNT_REG, g_uBulkInCount);
WrPktEp1(BulkInBuf, g_uBulkInCount);
g_uBulkInAddr = BaseAddr + g_uBulkInCount;
g_uBulkInCount = 0;
}
}
void HandleEvent_BulkIn(void)
{
UINT16 ep1csr;
UINT32 temp;
// EP1 CSR register status check
Outp32(INDEX_REG, 0x01);
Inp32(EP_STATUS_REG, ep1csr);
Outp32(EP_STATUS_REG, ep1csr);
Inp32(DMA_TOTAL_CNT1_REG, temp);
//EdbgOutputDebugString("EP1: DMA_TOTAL_CNT1_REG : %x\n", temp);
if (ep1csr & EP_SENT_STALL) { // SENT STALL : protocol stall.
//EdbgOutputDebugString("Sent Stall \n");
Outp32(EP_STATUS_REG, EP_SENT_STALL);
}
if (ep1csr & EP_TX_SUCCESS)
{
//EdbgOutputDebugString("EP1_TX_SUCCESS\n");
Outp32(EP_STATUS_REG, EP_TX_SUCCESS); // Endpoint Status Register Clear
if (g_eOpMode == USB_CPU)
{
if (g_uBulkInCount != 0)
PrepareEp1Fifo(g_uBulkInAddr);
}
}
if (DMA_TOTAL_COUNT_ZERO & ep1csr)
{
//EdbgOutputDebugString("USB_DMA_MODE, DMA TX Done(DMA_TOTAL_COUNT_ZERO) !!\n");
Outp32(DMA_CON_REG, DMA_TX_STOP|USB_INT_MODE);
Outp32(FCON, DMA_DISABLE);
}
}
void HandleEvent_BulkOut(void)
{
// UINT32 ReadData;
// UINT32 RecDataCnt;
UINT16 ep3csr;//, ep2con;//, sys_status;
UINT32 CBWSignature=0, CBWTag=0;//, i;
UINT8 TempBuf[16];
UINT16 fifoCnt;
UINT16 fifoCntByte;
// UINT32 DmaCurrAddr;
UINT32 temp;
UINT32 uUploadSize;
UINT32 uUploadAddr;
Outp32(INDEX_REG, EP3);
Inp32(EP_STATUS_REG, ep3csr);
Outp32(EP_STATUS_REG, ep3csr);
// DbgUsb(("Bulk Out Int, ep3csr : %x\n", ep3csr));
Inp32(DMA_TOTAL_CNT1_REG, temp);
//EdbgOutputDebugString("EP3: DMA_TOTAL_CNT1_REG : %x\n", temp);
if (ep3csr & EP_SENT_STALL) // SENT STALL : protocol stall.
{
// Uart_Printf(" Sent Stall \n");
Outp32(EP_STATUS_REG, EP_SENT_STALL);
return;
}
if (ep3csr & EP_FIFO_FLUSH)
{
Outp32(EP_CON_REG, EP_FIFO_FLUSH);
return;
}
if (ep3csr & EP_RX_SUCCESS)
{
//EdbgOutputDebugString("EP3_RX_PKT_SUCCESS\n");
/*
if (g_uDownloadFileSize==0)
{
Inp32(BYTE_READ_CNT_REG, fifoCnt);
if (fifoCnt == 5)
{
RdPktEp3((UINT8 *)TempBuf, 10);
temp = *((UINT8 *)(TempBuf+8))+
(*((UINT8 *)(TempBuf+9))<<8);
EdbgOutputDebugString("temp: %x\n", temp);
if (temp==0x1)
{
uUploadAddr =
*((UINT8 *)(TempBuf+0))+
(*((UINT8 *)(TempBuf+1))<<8)+
(*((UINT8 *)(TempBuf+2))<<16)+
(*((UINT8 *)(TempBuf+3))<<24);
uUploadSize =
*((UINT8 *)(TempBuf+4))+
(*((UINT8 *)(TempBuf+5))<<8)+
(*((UINT8 *)(TempBuf+6))<<16)+
(*((UINT8 *)(TempBuf+7))<<24);
//EdbgOutputDebugString("UploadAddress : %x, UploadSize: %x\n", uUploadAddr, uUploadSize);
if (g_eOpMode == USB_CPU)
{
//EdbgOutputDebugString("CPU_MODE Bulk In Function\n");
g_uBulkInCount = uUploadSize;
PrepareEp1Fifo(uUploadAddr);
}
else
{
//EdbgOutputDebugString("DMA_MODE Bulk In Function\n");
Outp32(FCON, DMA_ENABLE); // USB Dma Enable in Core Outside
Outp32(INDEX_REG, EP1); // IN Direction Device -> Host
Outp32(DMA_IF_CON_REG, MAX_BURST_INCR16);
Outp32(BYTE_WRITE_CNT_REG, g_uEp1MaxPktSize);
Outp32(MAX_PKT_REG, g_uEp1MaxPktSize);
Outp32(DMA_FIFO_CNT_REG, g_uEp1MaxPktSize);
Outp32(DMA_CNT_REG, g_uEp1MaxPktSize);
Outp32(DMA_MEM_BASE_ADDR, uUploadAddr);
Outp32(DMA_TOTAL_CNT1_REG, (UINT16)uUploadSize);
Outp32(DMA_TOTAL_CNT2_REG, (UINT16)(uUploadSize>>16));
Outp32(DMA_CON_REG, DMA_FLY_ENABLE|DMA_TX_START|USB_DMA_MODE);
}
}
g_uDownloadFileSize=0;
return;
}
else
{
// printf("^");
RdPktEp3((UINT8 *)TempBuf, 8);
if (ep3csr&(0x1<<4))
fifoCntByte = fifoCnt * 2 -1;
else
fifoCntByte = fifoCnt * 2;
//EdbgOutputDebugString("downloadFileSize==0, 1'st BYTE_READ_CNT_REG : %x\n", fifoCntByte);
g_uDownloadAddress=
*((UINT8 *)(TempBuf+0))+
(*((UINT8 *)(TempBuf+1))<<8)+
(*((UINT8 *)(TempBuf+2))<<16)+
(*((UINT8 *)(TempBuf+3))<<24);
g_uDownloadFileSize=
*((UINT8 *)(TempBuf+4))+
(*((UINT8 *)(TempBuf+5))<<8)+
(*((UINT8 *)(TempBuf+6))<<16)+
(*((UINT8 *)(TempBuf+7))<<24);
g_pDownPt=(UINT8 *)g_uDownloadAddress;
//EdbgOutputDebugString("downloadAddress : %x, downloadFileSize: %x\n", g_uDownloadAddress, g_uDownloadFileSize);
//printf("downloadAddress : %x, downloadFileSize: %x\n", g_uDownloadAddress, g_uDownloadFileSize));
downloadAddress =g_uDownloadAddress; // add by cha
downloadFileSize =g_uDownloadFileSize; // add by cha
RdPktEp3((UINT8 *)g_pDownPt, fifoCntByte-8); // The first 8-bytes are deleted.
if (g_eOpMode == USB_CPU)
{
if (ep3csr & (0x2<<2))
{
Inp32(BYTE_READ_CNT_REG, fifoCnt);
if (ep3csr&(0x1<<4))
fifoCntByte = fifoCnt * 2 -1;
else
fifoCntByte = fifoCnt * 2;
//EdbgOutputDebugString("2'd BYTE_READ_CNT_REG : %x\n", fifoCntByte);
RdPktEp3((UINT8 *)g_pDownPt, fifoCntByte);
}
}
else
{
Outp32(FCON, DMA_ENABLE); // USB Dma Enable in Core Outside
Outp32(INDEX_REG, EP3); // OUT Direction Host -> Device
Outp32(DMA_IF_CON_REG, MAX_BURST_INCR16);
Outp32(MAX_PKT_REG, g_uEp3MaxPktSize);
Outp32(DMA_FIFO_CNT_REG, g_uEp3MaxPktSize);
Outp32(DMA_CNT_REG, g_uEp3MaxPktSize);
Outp32(DMA_MEM_BASE_ADDR, g_uDownloadAddress+fifoCntByte-8);
Inp32(DMA_MEM_BASE_ADDR, temp);
//EdbgOutputDebugString("DMA_MEM_BASE_ADDR : %x\n", temp);
Outp32(DMA_TOTAL_CNT1_REG, (UINT16)(g_uDownloadFileSize-fifoCntByte));
Outp32(DMA_TOTAL_CNT2_REG, (UINT16)(g_uDownloadFileSize>>16));
//EdbgOutputDebugString("Out Direction DMA RX Start\n");
Outp32(DMA_CON_REG, DMA_FLY_ENABLE|DMA_RX_START|USB_DMA_MODE);
}
}
}
else*/
{
if (g_eOpMode == USB_CPU)
{
Inp32(BYTE_READ_CNT_REG, fifoCnt);
if (ep3csr&(0x1<<4))
fifoCntByte = fifoCnt * 2 -1;
else
fifoCntByte = fifoCnt * 2;
//EdbgOutputDebugString("downloadFileSize!=0, 0x%x 1'st BYTE_READ_CNT_REG : %x\n", g_pDownPt, fifoCntByte);
RdPktEp3((UINT8 *)g_pDownPt, fifoCntByte);
if (ep3csr & (0x2<<2))
{
Inp32(BYTE_READ_CNT_REG, fifoCnt);
if (ep3csr&(0x1<<4))
fifoCntByte = fifoCnt * 2 -1;
else
fifoCntByte = fifoCnt * 2;
//EdbgOutputDebugString("2'd BYTE_READ_CNT_REG : %x\n", fifoCntByte);
RdPktEp3((UINT8 *)g_pDownPt, fifoCntByte);
}
}
}
}
if (DMA_TOTAL_COUNT_ZERO & ep3csr)
{
//EdbgOutputDebugString("USB_DMA_MODE, DMA RX Done(DMA_TOTAL_COUNT_ZERO) !!\n");
Outp32(DMA_CON_REG, DMA_RX_STOP|USB_INT_MODE);
Outp32(FCON, DMA_DISABLE);
}
}
#define BIT_ALLMSK (0xffffffff)
#define BIT_USBD (0x1<<IRQ_USBD)
void Isr_Init(void)
{
volatile S3C2443_INTR_REG *s2443INT = (S3C2443_INTR_REG *)OALPAtoVA(S3C2443_BASE_REG_PA_INTR, FALSE);
s2443INT->INTMOD=0x0; // All=IRQ mode
s2443INT->INTMSK=BIT_ALLMSK; // All interrupt is masked.
// //EdbgOutputDebugString("INFO: (unsigned)IsrUsbd : 0x%x\r\n", (unsigned)IsrUsbd);
// //EdbgOutputDebugString("INFO: (unsigned)IsrHandler : 0x%x\r\n", (unsigned)IsrHandler);
// make value to assemble code "b IsrHandler"
// EdbgOutputDebugString("INFO: (unsigned)pISR : 0x%x\r\n", (unsigned)pISR);
pISR =(unsigned)(0xEA000000)+(((unsigned)IsrHandler - (0x80000000 + 0x18 + 0x8) )>>2);
// EdbgOutputDebugString("INFO: (unsigned)pISR : 0x%x\r\n", (unsigned)pISR);
// EdbgOutputDebugString("INFO: (unsigned)IsrHandler : 0x%x\r\n", (unsigned)IsrHandler);
if (s2443INT->SRCPND & BIT_USBD) s2443INT->SRCPND = BIT_USBD;
if (s2443INT->INTPND & BIT_USBD) s2443INT->INTPND = BIT_USBD;
s2443INT->INTMSK &= ~BIT_USBD; // USB Interrupt enable.
}
void IsrUsbd(unsigned int val)
{
volatile S3C2443_INTR_REG *s2443INT = (S3C2443_INTR_REG *)OALPAtoVA(S3C2443_BASE_REG_PA_INTR, FALSE);
UINT32 uStatus;
UINT16 ep_int_status, ep_int;
Inp32(SYS_STATUS_REG, uStatus); // System status read
//EdbgOutputDebugString("SYS_STATUS_REG : %x \n", uStatus);
if (uStatus & INT_REG_VBUS)
{
Outp32(SYS_STATUS_REG, INT_REG_VBUS); // Interrupt Clear
//EdbgOutputDebugString("\n [USB_Diag_Log] : INT_REG_VBUS\n");
}
if (uStatus & 0xff80) // Error interrupt check
{
Outp32(SYS_STATUS_REG, INT_ERR); // Interrupt Clear
//EdbgOutputDebugString("\n [USB_Diag_Log] : Error_INT\n");
}
// Which USB interrupts happen
if (uStatus & INT_REG_SUSPEND)
{
Outp32(SYS_STATUS_REG, INT_REG_SUSPEND); // Interrupt Clear
//EdbgOutputDebugString("\n [USB_Diag_Log] : Suspend Mode");
}
if (uStatus & INT_REG_RESUME)
{
Outp32(SYS_STATUS_REG, INT_REG_RESUME); // Host software send ClearPortFeature. Interrupt Clear
//EdbgOutputDebugString("\n [USB_Diag_Log] : Resume Mode \n");
}
if (uStatus & INT_REG_RESET) // Reset interrupt
{
Outp32(SYS_STATUS_REG, INT_REG_RESET); // Interrupt Clear
SetEndpoint();
g_uEp0State = EP0_STATE_INIT;
//EdbgOutputDebugString("\n [USB_Diag_Log] : Reset Mode \n");
}
if (uStatus & INT_REG_SDE) // Device Speed Detection interrupt
{
Outp32(SYS_STATUS_REG, INT_REG_SDE); // Interrupt Clear
//EdbgOutputDebugString("\n [USB_Diag_Log] : Speed Detection interrupt \n");
if (uStatus & INT_REG_HSP) // Set if Device is High speed or Full speed
{
Outp32(SYS_STATUS_REG, INT_REG_HSP); // High Speed Device Interrupt Clear?? may be not.
//EdbgOutputDebugString("\n [USB_Diag_Log] : High Speed Detection\n");
SetMaxPktSizes(USB_HIGH);
SetDescriptorTable();
}
else
{
SetMaxPktSizes(USB_FULL);
SetDescriptorTable();
}
}
Inp32(EP_STATUS_REG, ep_int_status); // EP interrrupt status read
//EdbgOutputDebugString("EP_STATUS_REG : %x \n", ep_int_status);
Inp32(EP_INT_REG, ep_int);
//EdbgOutputDebugString("EP_INT_REG : %x \n", ep_int);
if (ep_int & INT_REG_EP0)
{
//DbgUsb(("\n [USB_Diag_Log] : Control Transfer Interrupt \n"));
Outp32(EP_INT_REG, INT_REG_EP0); // Interrupt Clear
HandleEvent_EP0();
}
// Endpoint1 bulkIn
else if (ep_int & INT_REG_EP1)
{
Outp32(EP_INT_REG, INT_REG_EP1); // Interrupt Clear
// EdbgOutputDebugString("\n [USB_Diag_Log] : Ep1 Interrupt \n");
HandleEvent_BulkIn();
}
// Endpoint2 bulkOut
else if (ep_int & INT_REG_EP3)
{
// EdbgOutputDebugString("\n [USB_Diag_Log] : Bulk Out Transfer Interrupt \n");
Outp32(EP_INT_REG, INT_REG_EP3); // Interrupt Clear
// printf("*");
HandleEvent_BulkOut();
}
if (s2443INT->INTPND & BIT_USBD)
{
s2443INT->SRCPND = BIT_USBD;
if (s2443INT->INTPND & BIT_USBD) s2443INT->INTPND = BIT_USBD;
}
}
#pragma optimize ("",off)
BOOL UbootReadData(DWORD cbData, LPBYTE pbData)
{
volatile S3C2443_INTR_REG *s2443INT = (S3C2443_INTR_REG *)OALPAtoVA(S3C2443_BASE_REG_PA_INTR, FALSE);
//RETAILMSG(1,(TEXT("UbootReadData\n")));
while(1)
{
//RETAILMSG(1,(TEXT("0x%x 0x%x\n"), g_pDownPt, (readPtIndex + cbData)));
if ( g_pDownPt >= readPtIndex + cbData )
{
memcpy(pbData, readPtIndex, cbData);
readPtIndex += cbData;
break;
}
else if(g_pDownPt == DMABUFFER)
{
/*
if (s2443INT->SRCPND & BIT_USBD) s2443INT->SRCPND = BIT_USBD;
if (s2443INT->INTPND & BIT_USBD) s2443INT->INTPND = BIT_USBD;
s2443INT->INTMSK &= ~BIT_USBD; // USB Interrupt enable.
*/
}
}
return TRUE;
}
#pragma optimize ("",on)
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