📄 startup.s.svn-base
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;------------------------------------------------------------------------------
;
; File: startup.s
;
; Kernel startup routine for Samsung SMDK2443 board. Hardware is
; initialized in boot loader - so there isn't much code at all.
;
;------------------------------------------------------------------------------
INCLUDE kxarm.h
INCLUDE s3c2443.inc
IMPORT OALClearUTLB
IMPORT OALFlushICache
IMPORT OALFlushDCache
; Data Cache Characteristics.
;
DCACHE_LINES_PER_SET_BITS EQU 6
DCACHE_LINES_PER_SET EQU 64
DCACHE_NUM_SETS EQU 8
DCACHE_SET_INDEX_BIT EQU (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE EQU 32
SLEEPDATA_BASE_VIRTUAL EQU 0xA0028000 ; keep in sync w/ config.bib
SLEEPDATA_BASE_PHYSICAL EQU 0x30028000
SleepState_Data_Start EQU (0)
SleepState_WakeAddr EQU (SleepState_Data_Start )
SleepState_MMUCTL EQU (SleepState_WakeAddr + WORD_SIZE )
SleepState_MMUTTB EQU (SleepState_MMUCTL + WORD_SIZE )
SleepState_MMUDOMAIN EQU (SleepState_MMUTTB + WORD_SIZE )
SleepState_SVC_SP EQU (SleepState_MMUDOMAIN + WORD_SIZE )
SleepState_SVC_SPSR EQU (SleepState_SVC_SP + WORD_SIZE )
SleepState_FIQ_SPSR EQU (SleepState_SVC_SPSR + WORD_SIZE )
SleepState_FIQ_R8 EQU (SleepState_FIQ_SPSR + WORD_SIZE )
SleepState_FIQ_R9 EQU (SleepState_FIQ_R8 + WORD_SIZE )
SleepState_FIQ_R10 EQU (SleepState_FIQ_R9 + WORD_SIZE )
SleepState_FIQ_R11 EQU (SleepState_FIQ_R10 + WORD_SIZE )
SleepState_FIQ_R12 EQU (SleepState_FIQ_R11 + WORD_SIZE )
SleepState_FIQ_SP EQU (SleepState_FIQ_R12 + WORD_SIZE )
SleepState_FIQ_LR EQU (SleepState_FIQ_SP + WORD_SIZE )
SleepState_ABT_SPSR EQU (SleepState_FIQ_LR + WORD_SIZE )
SleepState_ABT_SP EQU (SleepState_ABT_SPSR + WORD_SIZE )
SleepState_ABT_LR EQU (SleepState_ABT_SP + WORD_SIZE )
SleepState_IRQ_SPSR EQU (SleepState_ABT_LR + WORD_SIZE )
SleepState_IRQ_SP EQU (SleepState_IRQ_SPSR + WORD_SIZE )
SleepState_IRQ_LR EQU (SleepState_IRQ_SP + WORD_SIZE )
SleepState_UND_SPSR EQU (SleepState_IRQ_LR + WORD_SIZE )
SleepState_UND_SP EQU (SleepState_UND_SPSR + WORD_SIZE )
SleepState_UND_LR EQU (SleepState_UND_SP + WORD_SIZE )
SleepState_SYS_SP EQU (SleepState_UND_LR + WORD_SIZE )
SleepState_SYS_LR EQU (SleepState_SYS_SP + WORD_SIZE )
SleepState_Data_End EQU (SleepState_SYS_LR + WORD_SIZE )
SLEEPDATA_SIZE EQU ((SleepState_Data_End - SleepState_Data_Start) / 4)
;---------------------------------------------------------------------------
;
; Macro to feed the LED Reg (The GPIO) with the value desired for debugging.
; Uses physical address
;
; GPFDAT [7:4] is assigned to LEDs.
MACRO
LED_ON $data
LDR r10, =GPFUDP
LDR r11, =0x5500 ;Pull-Up-Down Disable
STR r11, [r10]
LDR r10, = GPFCON
LDR r11, = (0x5500) ; GPF[7:4] Output .
STR r11, [r10]
LDR r10, =GPFDAT
LDR r11, =$data
MOV r11, r11, lsl #4 ; [7:4]
STR r11, [r10]
MEND
; LED_ON using virtual address
;
MACRO
VLED_ON $data
LDR r10, = vGPFUDP
LDR r11, =0x5500 ;Pull-Up-Down Disable
STR r11, [r10]
LDR r10, = vGPFCON
LDR r11, = (0x5500) ; GPF[7:4] Output .
STR r11, [r10]
LDR r10, =vGPFDAT
LDR r11, =$data
MOV r11, r11, lsl #4 ; [7:4]
STR r11, [r10]
MEND
;---------------------------------------------------------------------------
; IMPORT Max1718_Init
; IMPORT Max1718_Set
IMPORT KernelStart
TEXTAREA
; Include memory configuration file with g_oalAddressTable
LEAF_ENTRY StartUp
; Compute the OEMAddressTable's physical address and
; load it into r0. KernelStart expects r0 to contain
; the physical address of this table. The MMU isn't
; turned on until well into KernelStart.
; Jump over power-off code.
1 b ResetHandler
b %B1 ;HandlerUndef ;handler for Undefined mode
b %B1 ;HandlerSWI ;handler for SWI interrupt
b %B1 ;HandlerPabort ;handler for PAbort
b %B1 ;HandlerDabort ;handler for DAbort
b %B1 ; ;reserved
b %B1 ;HandlerIRQ ;handler for IRQ interrupt
b %B1 ;HandlerFIQ ;handler for FIQ interrupt
ResetHandler
ldr r0, =WTCON ; disable the watchdog timer.
mov r1,#0
str r1, [r0]
;;;;;;;;;;;; set voltage test
;bl Max1718_Init
;mov r0, #0x1
;mov r1, #120
;mov r1, #125
;mov r1, #130
;mov r1, #135
;bl Max1718_Set
; ldr r0, =EBICON ; EBI
; ldr r1, =EBICON_VAL ; Refer s3c2443.inc
; str r1,[r0]
ldr r0, = GPFCON
ldr r1, = 0x5500
str r1, [r0]
ldr r0, =INTMSK ; mask all first-level interrupts.
ldr r1, =0xffffffff
str r1, [r0]
ldr r0, =INTSUBMSK ; mask all second-level interrupts.
ldr r1, =0x1fffffff
str r1, [r0]
ldr r0, = INTMOD
mov r1, #0x0 ; set all interrupt as IRQ
str r1, [r0]
LED_ON 0x2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; When the Eboot is already, No need to set again.
;; IF set as "FALSE", The FCLK,HCLK,PCLK Clock will detect automatically in OS.
;; IF set as "TRUE", The FCLK,HCLK,PCLK Clock and Memory setting will be set again here and detect automatically in OS.
[ CHANGE_CLK_OAL=1 ; Refer the S3c2443.inc.
LED_ON 0x3
ldr r0,=CLKDIV0 ; Set Clock Divider
ldr r1,[r0]
bic r1,r1,#0x37 ; clear HCLKDIV, PREDIV, PCLKDIV
bic r1,r1,#(0xf<<9) ; clear ARMCLKDIV
ldr r2,=((Startup_ARMCLKdiv<<9)+(Startup_PREdiv<<4)+(Startup_PCLKdiv<<2)+(Startup_HCLKdiv))
orr r1,r1,r2
str r1,[r0]
LED_ON 0x4
ldr r0,=LOCKCON0 ; Set lock time of MPLL. added by junon
mov r1,#0xe10 ; Fin = 12MHz - 0x800, 16.9844MHz - 0xA00
str r1,[r0]
ldr r0,=LOCKCON1 ; Set lock time of EPLL. added by junon
mov r1,#0x800 ; Fin = 12MHz - 0x800, 16.9844MHz - 0xA00
str r1,[r0]
ldr r0,=MPLLCON ; Set MPLL
ldr r1,=((0<<24)+(Startup_Mdiv<<16)+(Startup_Pdiv<<8)+(Startup_Sdiv))
str r1,[r0]
ldr r0,=EPLLCON ; Set EPLL
ldr r1,=((0<<24)+(Startup_EMdiv<<16)+(Startup_EPdiv<<8)+(Startup_ESdiv))
str r1,[r0]
LED_ON 0x5
ldr r0,=CLKSRC ; Select MPLL clock out for SYSCLK
ldr r1,[r0]
orr r1,r1,#0x50
str r1,[r0]
;bl MMU_SetAsyncBusMode
LED_ON 0x7
bl InitSSMC
] ; End of PLL setting
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
[ DVSON = 1
; bl DVS_ON
; ldr r0,=CLKDIV0 ; Set DVS
; ldr r1,[r0]
; orr r1,r1,#0x2000
; str r1,[r0]
]
bl MMU_SetAsyncBusMode
; :::::::::::::::::::::::::::::::::::::::::::::
; Add for Power Management
; - - - - - - - - - - - - - - - - - - - - - - -
[ {TRUE}
ldr r1, =RSTSTAT ; Determine Booting Mode
ldr r0, [r1]
tst r0, #0x8 ; Power-Off reset Check
beq %f4
ldr r5, =SLEEPDATA_BASE_PHYSICAL ; pointer to physical address of reserved Sleep mode info data structure
mov r3, r5 ; pointer for checksum calculation
mov r2, #0
ldr r0, =SLEEPDATA_SIZE ; get size of data structure to do checksum on
40
ldr r1, [r3], #4 ; pointer to SLEEPDATA
and r1, r1, #0x1
mov r1, r1, LSL #31
orr r1, r1, r1, LSR #1
add r2, r2, r1
subs r0, r0, #1 ; dec the count
bne %b40 ; loop till done
ldr r0,=INFORM3
ldr r3, [r0] ; get the Sleep data checksum from the Power Manager Scratch pad register
teq r2, r3 ; compare to what we saved before going to sleep
bne JumpToRAM ; bad news - do a cold boot - If emergency power off case, normal booting.
b MMUENABLE
JumpToRAM
ldr r2, =0x200000 ;=0x201000 ; offset into the RAM
ldr r3, =0x30000000 ; add physical base
add r2, r2, r3
mov pc, r2 ; & jump to StartUp address
MMUENABLE
; 2. MMU Enable
ldr r10, [r5, #SleepState_MMUDOMAIN] ; load the MMU domain access info
ldr r9, [r5, #SleepState_MMUTTB] ; load the MMU TTB info
ldr r8, [r5, #SleepState_MMUCTL] ; load the MMU control info
ldr r7, [r5, #SleepState_WakeAddr] ; load the LR address
nop
nop
nop
nop
nop
; wakeup routine
1
mcr p15, 0, r10, c3, c0, 0 ; setup access to domain 0
mcr p15, 0, r9, c2, c0, 0 ; PT address
mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
mcr p15, 0, r8, c1, c0, 0 ; restore MMU control
; 3. Jump to Kernel Image's fw.s(Awake_address)
mov pc, r7 ; & jump to new virtual address (back up Power management stack)
nop
]
4
;;;;;;;;;;;;;;;;;; set clkout1 - HCLK
ldr r0,=MISCCR
ldr r1,[r0]
bic r1,r1, #0x770
orr r1,r1,#0x320
str r1,[r0]
ldr r0,=GPHUDP
ldr r1,[r0]
bic r1,r1, #0x3C000000
orr r1,r1, #0x14000000
str r1,[r0]
ldr r0,=GPHCON
ldr r1,[r0]
bic r1,r1, #0x3C000000
orr r1,r1, #0x28000000
str r1,[r0]
;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;; PWR & CLK OFF FOR TEST
; ldr r0,=HCLKCON
; ldr r1,=0xFFFFFFFF ;0xFFFCE0FF ;0xFFFCF6FF
; str r1,[r0]
; ldr r0,=PCLKCON
; ldr r1,=0xFFFF3F82 ;0xFFFF3E02 ;0xFFFF3F82
; str r1,[r0]
; ldr r0,=SCLKCON
; ldr r1,=0xFFFF87FD ;0xFFFE83FD ;0xFFFF87FD
; str r1,[r0]
;;;;;;;;;;;;;;;;;;
; LED_ON 0x8
add r0, pc, #g_oalAddressTable - (. + 8)
bl KernelStart ; Call the WinCE kernel.
LTORG
INCLUDE oemaddrtab_cfg.inc
ENTRY_END
LEAF_ENTRY OALCPUPowerOff
; 1. Push SVC state onto our stack
stmdb sp!, {r4-r12}
stmdb sp!, {lr}
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