cxa2069.h

音视频切换IC CXA2069处理芯片应用代码。

/************************************************************
 Copyright (C), 2007-2008, Xugang Tech. Co., Ltd.
 FileName: CXA2069.H
 Description: CXA2069处理函数头文件

 Others:

 IC: MB90F882

 History: // 历史修改记录
 <author>     <time>        <version >         <desc>
 Huangs      2008-06-17         1.0         build this moudle
***********************************************************/

#ifndef __CXA2069_H
#define __CXA2069_H

#include "TYPEDEF.H"


/*******************************************************************************
Control register structure (DATA1 to DATA3)
? All registers are set to “0” during IC power on.
? “*” indicates undefined.
--------------------------------------------------------------------------------
          |   b7    |  b6    |  b5  |    b4      b3      b2      b1       b0   |
--------------------------------------------------------------------------------
Slave add.|   1     |  0     |  0   |    1    |    0    | 0   |   ADR   |  R/W |
--------------------------------------------------------------------------------
DATA1     |  A-GAIN | S/COMP1|          V-IN1           |        A-IN1         |
--------------------------------------------------------------------------------
DATA2     |  V/YOUT | S/COMP2|          V-IN2           |        A-IN2         |
--------------------------------------------------------------------------------
DATA3     |     *   | S/COMP3|          AV-IN3          |        DC OUT |    * |
--------------------------------------------------------------------------------

*******************************************************************************/

#define ADDR_CXA2069        0x90 
                       /* when the ADR Pin set high, the addr. is 0x92 */

extern UCHAR   guchv_avOut1Bak;

extern __direct union CXA2069_STD1 guuv_sCXA2069;

#define guuv_statusCXA2069      guuv_sCXA2069.byte

#define CXA2069_A_GAIN          guuv_sCXA2069.sbyte.A_GAIN
#define CXA2069_S_COMP1         guuv_sCXA2069.sbyte.S_COMP1
#define CXA2069_V_IN1           guuv_sCXA2069.sbyte.V_IN1
#define CXA2069_A_IN1           guuv_sCXA2069.sbyte.A_IN1

#define CXA2069_V_YOUT          guuv_sCXA2069.sbyte.V_YOUT
#define CXA2069_S_COMP2         guuv_sCXA2069.sbyte.S_COMP2
#define CXA2069_V_IN2           guuv_sCXA2069.sbyte.V_IN2
#define CXA2069_A_IN2           guuv_sCXA2069.sbyte.A_IN2

#define CXA2069_S_COMP3         guuv_sCXA2069.sbyte.S_COMP3
#define CXA2069_AV_IN3          guuv_sCXA2069.sbyte.AV_IN3
#define CXA2069_DC_OUT          guuv_sCXA2069.sbyte.DC_OUT

/*********** V-IN1 SELECTION ******************/

#define SEL_V1MUTE        0
#define SEL_V1CH0_IN      1   /* TV INPUT */
#define SEL_V1CH1_IN      2   /* V1 AND Y1/C1 INPUTS */
#define SEL_V1CH2_IN      3   /* V2 AND Y2/C2 INPUTS */
#define SEL_V1CH3_IN      4   /* V3 AND Y3/C3 INPUTS */
#define SEL_V1CH4_IN      5   /* V4 AND Y4/C4 INPUTS */
#define SEL_V1CH5_IN      6   /* V5 INPUTS */
#define SEL_V1CH6_IN      7   /* V6 INPUTS */

/***********  V-IN2 SELECTION ******************/

#define SEL_V2MUTE        0
#define SEL_V2CH0_IN      1   /* TV INPUT */
#define SEL_V2CH1_IN      2   /* V1 AND Y1/C1 INPUTS */
#define SEL_V2CH2_IN      3   /* V2 AND Y2/C2 INPUTS */
#define SEL_V2CH3_IN      4   /* V3 AND Y3/C3 INPUTS */
#define SEL_V2CH4_IN      5   /* V4 AND Y4/C4 INPUTS */
#define SEL_V2CH5_IN      6   /* V5 INPUTS */
#define SEL_V2CH6_IN      7   /* V6 INPUTS */

/*********** A-IN1 SELECTION ******************/

#define SEL_A1MUTE        0
#define SEL_A1CH0_IN      1   /* LTV/RTV INPUT */
#define SEL_A1CH1_IN      2   /* LV1/RV1 INPUTS */
#define SEL_A1CH2_IN      3   /* LV2/RV2 INPUTS */
#define SEL_A1CH3_IN      4   /* LV3/RV3 INPUTS */
#define SEL_A1CH4_IN      5   /* LV4/RV4 INPUTS */
#define SEL_A1CH5_IN      6   /* LV5/RV5 INPUTS */
#define SEL_A1CH6_IN      7   /* LV6/RV6 INPUTS */

/*********** A-IN2 SELECTION ******************/

#define SEL_A2MUTE        0
#define SEL_A2CH0_IN      1   /* LTV/RTV INPUT */
#define SEL_A2CH1_IN      2   /* LV1/RV1 INPUTS */
#define SEL_A2CH2_IN      3   /* LV2/RV2 INPUTS */
#define SEL_A2CH3_IN      4   /* LV3/RV3 INPUTS */
#define SEL_A2CH4_IN      5   /* LV4/RV4 INPUTS */
#define SEL_A2CH5_IN      6   /* LV5/RV5 INPUTS */
#define SEL_A2CH6_IN      7   /* LV6/RV6 INPUTS */

/*********** AV-IN3 SELECTION ******************/

#define SEL_AV3MUTE        0
#define SEL_AV3CH0_IN      1   /* TV AND LTV/RTV INPUT */
#define SEL_AV3CH1_IN      2   /* V1 AND LV1/RV1 AND Y1/C1 INPUTS */
#define SEL_AV3CH2_IN      3   /* V2 AND LV2/RV2 AND Y2/C2 INPUTS */
#define SEL_AV3CH3_IN      4   /* V3 AND LV3/RV3 AND Y3/C3 INPUTS */
#define SEL_AV3CH4_IN      5   /* V4 AND LV4/RV4 AND Y4/C4 INPUTS */
#define SEL_AV3CH5_IN      6   /* V5 AND LV5/RV5 INPUTS */
#define SEL_AV3CH6_IN      7   /* V6 AND LV6/RV6 INPUTS */

/*********** DC-OUT SELECTION ******************/

#define SEL_DC_OUT_4V5      0
#define SEL_DC_OUT_0V       1
#define SEL_DC_OUT_1V9      2
#define SEL_DC_OUT1_4V5     3

/*********** Pin 44 (V/YOUT2) SELECTION ******************/

#define SEL_V_OUT           0   /* composite signal output */
#define SEL_Y_OUT           1   /* luminance signal output */

/*********** S/COMP1 to S/COMP3 SELECTION ******************/

#define SEL_CMP_SIGNAL_INPUT    0 /* Composite signal inputs 
                                    (TV, V1 to V6 inputs) */
#define SEL_S_TERMINAL_INPUT    1 /* S terminal inputs 
                                    (Y1/C1 to Y4/C4 inputs) */
/*********** A-GAIN SELECTION ******************/

#define SEL_0DB_GAIN            0 /* 0  dB output */
#define SEL_6DB_GAIN            1 /* -6 dB output */

/************ SYSTEM INPUTS ************************/

#define SEL_AUX2_IN             1
#define SEL_GPS_AUDIO           2
#define SEL_GPS_MAIN_VIDEO      2
#define SEL_BACK_CAMERA         3
#define SEL_RADIO_AUDIO_IN      3
#define SEL_IPOD_AV_IN          4
#define SEL_SERVO_AV_IN         5
#define SEL_TV_DVB_AV_IN        6
#define SEL_AUX1_IN             7

#endif