📄 gpif.lst
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167 /* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
168 /* Output*/ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
169 /* LFun */ 0x00, 0x09, 0x12, 0x12, 0x00, 0x2D, 0x12, 0x3F,
170 // Wave 1
171 /* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
172 /* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
173 /* Output*/ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
174 /* LFun */ 0x09, 0x09, 0x12, 0x12, 0x00, 0x2D, 0x36, 0x3F,
175 // Wave 2
176 /* LenBr */ 0x05, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
177 /* Opcode*/ 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
178 /* Output*/ 0xFF, 0xE7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
179 /* LFun */ 0x00, 0x09, 0x12, 0x3F, 0x00, 0x2D, 0x12, 0x3F,
C51 COMPILER V7.02b GPIF 07/11/2004 12:05:28 PAGE 4
180 // Wave 3
181 /* LenBr */ 0x05, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
182 /* Opcode*/ 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
183 /* Output*/ 0xFF, 0xD7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
184 /* LFun */ 0x09, 0x09, 0x12, 0x3F, 0x00, 0x2D, 0x36, 0x3F
185 };
186 // END DO NOT EDIT
187
188 // DO NOT EDIT ...
189 const char xdata InitData[7] =
190 {
191 /* Regs */ 0x80,0x00,0x00,0xFF,0x06,0xE4,0x11
192 };
193 // END DO NOT EDIT
194
195 // TO DO: You may add additional code below.
196
197 void GpifInit( void )
198 {
199 1 BYTE i;
200 1
201 1 // Registers which require a synchronization delay, see section 15.14
202 1 // FIFORESET FIFOPINPOLAR
203 1 // INPKTEND OUTPKTEND
204 1 // EPxBCH:L REVCTL
205 1 // GPIFTCB3 GPIFTCB2
206 1 // GPIFTCB1 GPIFTCB0
207 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
208 1 // EPxFIFOCFG EPxGPIFFLGSEL
209 1 // PINFLAGSxx EPxFIFOIRQ
210 1 // EPxFIFOIE GPIFIRQ
211 1 // GPIFIE GPIFADRH:L
212 1 // UDMACRCH:L EPxGPIFTRIG
213 1 // GPIFTRIG
214 1
215 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
216 1 // ...these have been replaced by GPIFTC[B3:B0] registers
217 1
218 1 // 8051 doesn't have access to waveform memories 'til
219 1 // the part is in GPIF mode.
220 1
221 1 IFCONFIG = 0xCE;
222 1 // IFCLKSRC=1 , FIFOs executes on internal clk source
223 1 // xMHz=1 , 48MHz internal clk rate
224 1 // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
225 1 // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
226 1 // ASYNC=1 , master samples asynchronous
227 1 // GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
228 1 // IFCFG[1:0]=10, FX2 in GPIF master mode
229 1
230 1 GPIFABORT = 0xFF; // abort any waveforms pending
231 1
232 1 GPIFREADYCFG = InitData[ 0 ];
233 1 GPIFCTLCFG = InitData[ 1 ];
234 1 GPIFIDLECS = InitData[ 2 ];
235 1 GPIFIDLECTL = InitData[ 3 ];
236 1 GPIFWFSELECT = InitData[ 5 ];
237 1 GPIFREADYSTAT = InitData[ 6 ];
238 1
239 1 // use dual autopointer feature...
240 1 AUTOPTRSETUP = 0x07; // inc both pointers,
241 1 // ...warning: this introduces pdata hole(s)
C51 COMPILER V7.02b GPIF 07/11/2004 12:05:28 PAGE 5
242 1 // ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
243 1
244 1 // source
245 1 APTR1H = MSB( &WaveData );
246 1 APTR1L = LSB( &WaveData );
247 1
248 1 // destination
249 1 AUTOPTRH2 = 0xE4;
250 1 AUTOPTRL2 = 0x00;
251 1
252 1 // transfer
253 1 for ( i = 0x00; i < 128; i++ )
254 1 {
255 2 EXTAUTODAT2 = EXTAUTODAT1;
256 2 }
257 1
258 1
259 1
260 1 // Configure GPIF Address pins, output initial value,
261 1 PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
262 1 OEC = 0xFF; // and as outputs
263 1 PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
264 1 OEE |= 0x80; // and as output
265 1
266 1 // ...OR... tri-state GPIFADR[8:0] pins
267 1 // PORTCCFG = 0x00; // [7:0] as port I/O
268 1 // OEC = 0x00; // and as inputs
269 1 // PORTECFG &= 0x7F; // [8] as port I/O
270 1 // OEE &= 0x7F; // and as input
271 1
272 1 // GPIF address pins update when GPIFADRH/L written
273 1 SYNCDELAY; //
274 1 GPIFADRH = 0x00; // bits[7:1] always 0
275 1 SYNCDELAY; //
276 1 GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
277 1 }
278
279 #define TESTING_GPIF // NOTE: Comment this line out for frameworks based firmware
280 // See the example GPIF Tool Utility under Application
281 // Reference Material for more advanced development info
282 #ifdef TESTING_GPIF
283 // TODO: You may add additional code below.
284
285 void OtherInit( void )
286 { // interface initialization
287 1 // ...see TD_Init( );
288 1 }
289
290 // Set Address GPIFADR[8:0] to PERIPHERAL
291 void Peripheral_SetAddress( WORD gaddr )
292 {
293 1 SYNCDELAY; //
294 1 GPIFADRH = gaddr >> 8;
295 1 SYNCDELAY; //
296 1 GPIFADRL = ( BYTE )gaddr; // setup GPIF address
297 1 }
298
299 // Set EP2GPIF Transaction Count
300 void Peripheral_SetEP2GPIFTC( WORD xfrcnt )
301 {
302 1 SYNCDELAY; //
303 1 EP2GPIFTCH = xfrcnt >> 8; // setup transaction count
C51 COMPILER V7.02b GPIF 07/11/2004 12:05:28 PAGE 6
304 1 SYNCDELAY; //
305 1 EP2GPIFTCL = ( BYTE )xfrcnt;
306 1 }
307
308 // Set EP4GPIF Transaction Count
309 void Peripheral_SetEP4GPIFTC( WORD xfrcnt )
310 {
311 1 SYNCDELAY; //
312 1 EP4GPIFTCH = xfrcnt >> 8; // setup transaction count
313 1 SYNCDELAY; //
314 1 EP4GPIFTCL = ( BYTE )xfrcnt;
315 1 }
316
317 // Set EP6GPIF Transaction Count
318 void Peripheral_SetEP6GPIFTC( WORD xfrcnt )
319 {
320 1 SYNCDELAY; //
321 1 EP6GPIFTCH = xfrcnt >> 8; // setup transaction count
322 1 SYNCDELAY; //
323 1 EP6GPIFTCL = ( BYTE )xfrcnt;
324 1 }
325
326 // Set EP8GPIF Transaction Count
327 void Peripheral_SetEP8GPIFTC( WORD xfrcnt )
328 {
329 1 SYNCDELAY; //
330 1 EP8GPIFTCH = xfrcnt >> 8; // setup transaction count
331 1 SYNCDELAY; //
332 1 EP8GPIFTCL = ( BYTE )xfrcnt;
333 1 }
334
335 #define GPIF_FLGSELPF 0
336 #define GPIF_FLGSELEF 1
337 #define GPIF_FLGSELFF 2
338
339 // Set EP2GPIF Decision Point FIFO Flag Select (PF, EF, FF)
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