📄 at91sam7a3.inc
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;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_PITC
PITC_PIMR # 4 ;- Period Interval Mode Register
PITC_PISR # 4 ;- Period Interval Status Register
PITC_PIVR # 4 ;- Period Interval Value Register
PITC_PIIR # 4 ;- Period Interval Image Register
;- -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
AT91C_PITC_PIV EQU (0xFFFFF:SHL:0) ;- (PITC) Periodic Interval Value
AT91C_PITC_PITEN EQU (0x1:SHL:24) ;- (PITC) Periodic Interval Timer Enabled
AT91C_PITC_PITIEN EQU (0x1:SHL:25) ;- (PITC) Periodic Interval Timer Interrupt Enable
;- -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
AT91C_PITC_PITS EQU (0x1:SHL:0) ;- (PITC) Periodic Interval Timer Status
;- -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
AT91C_PITC_CPIV EQU (0xFFFFF:SHL:0) ;- (PITC) Current Periodic Interval Value
AT91C_PITC_PICNT EQU (0xFFF:SHL:20) ;- (PITC) Periodic Interval Counter
;- -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_WDTC
WDTC_WDCR # 4 ;- Watchdog Control Register
WDTC_WDMR # 4 ;- Watchdog Mode Register
WDTC_WDSR # 4 ;- Watchdog Status Register
;- -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
AT91C_WDTC_WDRSTT EQU (0x1:SHL:0) ;- (WDTC) Watchdog Restart
AT91C_WDTC_KEY EQU (0xFF:SHL:24) ;- (WDTC) Watchdog KEY Password
;- -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
AT91C_WDTC_WDV EQU (0xFFF:SHL:0) ;- (WDTC) Watchdog Timer Restart
AT91C_WDTC_WDFIEN EQU (0x1:SHL:12) ;- (WDTC) Watchdog Fault Interrupt Enable
AT91C_WDTC_WDRSTEN EQU (0x1:SHL:13) ;- (WDTC) Watchdog Reset Enable
AT91C_WDTC_WDRPROC EQU (0x1:SHL:14) ;- (WDTC) Watchdog Timer Restart
AT91C_WDTC_WDDIS EQU (0x1:SHL:15) ;- (WDTC) Watchdog Disable
AT91C_WDTC_WDD EQU (0xFFF:SHL:16) ;- (WDTC) Watchdog Delta Value
AT91C_WDTC_WDDBGHLT EQU (0x1:SHL:28) ;- (WDTC) Watchdog Debug Halt
AT91C_WDTC_WDIDLEHLT EQU (0x1:SHL:29) ;- (WDTC) Watchdog Idle Halt
;- -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
AT91C_WDTC_WDUNF EQU (0x1:SHL:0) ;- (WDTC) Watchdog Underflow
AT91C_WDTC_WDERR EQU (0x1:SHL:1) ;- (WDTC) Watchdog Error
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Memory Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_MC
MC_RCR # 4 ;- MC Remap Control Register
MC_ASR # 4 ;- MC Abort Status Register
MC_AASR # 4 ;- MC Abort Address Status Register
# 4 ;- Reserved
MC_PUIA # 64 ;- MC Protection Unit Area
MC_PUP # 4 ;- MC Protection Unit Peripherals
MC_PUER # 4 ;- MC Protection Unit Enable Register
# 8 ;- Reserved
MC_FMR # 4 ;- MC Flash Mode Register
MC_FCR # 4 ;- MC Flash Command Register
MC_FSR # 4 ;- MC Flash Status Register
;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
AT91C_MC_RCB EQU (0x1:SHL:0) ;- (MC) Remap Command Bit
;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
AT91C_MC_UNDADD EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status
AT91C_MC_MISADD EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status
AT91C_MC_MPU EQU (0x1:SHL:2) ;- (MC) Memory protection Unit Abort Status
AT91C_MC_ABTSZ EQU (0x3:SHL:8) ;- (MC) Abort Size Status
AT91C_MC_ABTSZ_BYTE EQU (0x0:SHL:8) ;- (MC) Byte
AT91C_MC_ABTSZ_HWORD EQU (0x1:SHL:8) ;- (MC) Half-word
AT91C_MC_ABTSZ_WORD EQU (0x2:SHL:8) ;- (MC) Word
AT91C_MC_ABTTYP EQU (0x3:SHL:10) ;- (MC) Abort Type Status
AT91C_MC_ABTTYP_DATAR EQU (0x0:SHL:10) ;- (MC) Data Read
AT91C_MC_ABTTYP_DATAW EQU (0x1:SHL:10) ;- (MC) Data Write
AT91C_MC_ABTTYP_FETCH EQU (0x2:SHL:10) ;- (MC) Code Fetch
AT91C_MC_MST0 EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source
AT91C_MC_MST1 EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source
AT91C_MC_SVMST0 EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source
AT91C_MC_SVMST1 EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source
;- -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
AT91C_MC_PROT EQU (0x3:SHL:0) ;- (MC) Protection
AT91C_MC_PROT_PNAUNA EQU (0x0) ;- (MC) Privilege: No Access, User: No Access
AT91C_MC_PROT_PRWUNA EQU (0x1) ;- (MC) Privilege: Read/Write, User: No Access
AT91C_MC_PROT_PRWURO EQU (0x2) ;- (MC) Privilege: Read/Write, User: Read Only
AT91C_MC_PROT_PRWURW EQU (0x3) ;- (MC) Privilege: Read/Write, User: Read/Write
AT91C_MC_SIZE EQU (0xF:SHL:4) ;- (MC) Internal Area Size
AT91C_MC_SIZE_1KB EQU (0x0:SHL:4) ;- (MC) Area size 1KByte
AT91C_MC_SIZE_2KB EQU (0x1:SHL:4) ;- (MC) Area size 2KByte
AT91C_MC_SIZE_4KB EQU (0x2:SHL:4) ;- (MC) Area size 4KByte
AT91C_MC_SIZE_8KB EQU (0x3:SHL:4) ;- (MC) Area size 8KByte
AT91C_MC_SIZE_16KB EQU (0x4:SHL:4) ;- (MC) Area size 16KByte
AT91C_MC_SIZE_32KB EQU (0x5:SHL:4) ;- (MC) Area size 32KByte
AT91C_MC_SIZE_64KB EQU (0x6:SHL:4) ;- (MC) Area size 64KByte
AT91C_MC_SIZE_128KB EQU (0x7:SHL:4) ;- (MC) Area size 128KByte
AT91C_MC_SIZE_256KB EQU (0x8:SHL:4) ;- (MC) Area size 256KByte
AT91C_MC_SIZE_512KB EQU (0x9:SHL:4) ;- (MC) Area size 512KByte
AT91C_MC_SIZE_1MB EQU (0xA:SHL:4) ;- (MC) Area size 1MByte
AT91C_MC_SIZE_2MB EQU (0xB:SHL:4) ;- (MC) Area size 2MByte
AT91C_MC_SIZE_4MB EQU (0xC:SHL:4) ;- (MC) Area size 4MByte
AT91C_MC_SIZE_8MB EQU (0xD:SHL:4) ;- (MC) Area size 8MByte
AT91C_MC_SIZE_16MB EQU (0xE:SHL:4) ;- (MC) Area size 16MByte
AT91C_MC_SIZE_64MB EQU (0xF:SHL:4) ;- (MC) Area size 64MByte
AT91C_MC_BA EQU (0x3FFFF:SHL:10) ;- (MC) Internal Area Base Address
;- -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
;- -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
AT91C_MC_PUEB EQU (0x1:SHL:0) ;- (MC) Protection Unit enable Bit
;- -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
AT91C_MC_EOP EQU (0x1:SHL:0) ;- (MC) End Of Programming Flag
AT91C_MC_EOL EQU (0x1:SHL:1) ;- (MC) End Of Lock/Unlock Flag
AT91C_MC_LOCKE EQU (0x1:SHL:2) ;- (MC) Lock Error Flag
AT91C_MC_PROGE EQU (0x1:SHL:3) ;- (MC) Programming Error Flag
AT91C_MC_NEBP EQU (0x1:SHL:7) ;- (MC) No Erase Before Programming
AT91C_MC_FWS EQU (0x3:SHL:8) ;- (MC) Flash Wait State
AT91C_MC_FWS_0FWS EQU (0x0:SHL:8) ;- (MC) 1 cycle for Read, 2 for Write operations
AT91C_MC_FWS_1FWS EQU (0x1:SHL:8) ;- (MC) 2 cycles for Read, 3 for Write operations
AT91C_MC_FWS_2FWS EQU (0x2:SHL:8) ;- (MC) 3 cycles for Read, 4 for Write operations
AT91C_MC_FWS_3FWS EQU (0x3:SHL:8) ;- (MC) 4 cycles for Read, 4 for Write operations
AT91C_MC_FMCN EQU (0xFF:SHL:16) ;- (MC) Flash Microsecond Cycle Number
;- -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
AT91C_MC_FCMD EQU (0xF:SHL:0) ;- (MC) Flash Command
AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
AT91C_MC_PAGEN EQU (0x3FF:SHL:8) ;- (MC) Page Number
AT91C_MC_KEY EQU (0xFF:SHL:24) ;- (MC) Writing Protect Key
;- -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
AT91C_MC_LOCKS0 EQU (0x1:SHL:16) ;- (MC) Sector 0 Lock Status
AT91C_MC_LOCKS1 EQU (0x1:SHL:17) ;- (MC) Sector 1 Lock Status
AT91C_MC_LOCKS2 EQU (0x1:SHL:18) ;- (MC) Sector 2 Lock Status
AT91C_MC_LOCKS3 EQU (0x1:SHL:19) ;- (MC) Sector 3 Lock Status
AT91C_MC_LOCKS4 EQU (0x1:SHL:20) ;- (MC) Sector 4 Lock Status
AT91C_MC_LOCKS5 EQU (0x1:SHL:21) ;- (MC) Sector 5 Lock Status
AT91C_MC_LOCKS6 EQU (0x1:SHL:22) ;- (MC) Sector 6 Lock Status
AT91C_MC_LOCKS7 EQU (0x1:SHL:23) ;- (MC) Sector 7 Lock Status
AT91C_MC_LOCKS8 EQU (0x1:SHL:24) ;- (MC) Sector 8 Lock Status
AT91C_MC_LOCKS9 EQU (0x1:SHL:25) ;- (MC) Sector 9 Lock Status
AT91C_MC_LOCKS10 EQU (0x1:SHL:26) ;- (MC) Sector 10 Lock Status
AT91C_MC_LOCKS11 EQU (0x1:SHL:27) ;- (MC) Sector 11 Lock Status
AT91C_MC_LOCKS12 EQU (0x1:SHL:28) ;- (MC) Sector 12 Lock Status
AT91C_MC_LOCKS13 EQU (0x1:SHL:29) ;- (MC) Sector 13 Lock Status
AT91C_MC_LOCKS14 EQU (0x1:SHL:30) ;- (MC) Sector 14 Lock Status
AT91C_MC_LOCKS15 EQU (0x1:SHL:31) ;- (MC) Sector 15 Lock Status
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface
;- *****************************************************************************
^ 0 ;- AT91S_CAN_MB
CAN_MB_MMR # 4 ;- MailBox Mode Register
CAN_MB_MAM # 4 ;- MailBox Acceptance Mask Register
CAN_MB_MID # 4 ;- MailBox ID Register
CAN_MB_MFID # 4 ;- MailBox Family ID Register
CAN_MB_MSR # 4 ;- MailBox Status Register
CAN_MB_MDL # 4 ;- MailBox Data Low Register
CAN_MB_MDH # 4 ;- MailBox Data High Register
CAN_MB_MCR # 4 ;- MailBox Control Register
;- -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register --------
AT91C_CAN_MTIMEMARK EQU (0xFFFF:SHL:0) ;- (CAN_MB) Mailbox Timemark
AT91C_CAN_PRIOR EQU (0xF:SHL:16) ;- (CAN_MB) Mailbox Priority
AT91C_CAN_MOT EQU (0x7:SHL:24) ;- (CAN_MB) Mailbox Object Type
AT91C_CAN_MOT_DIS EQU (0x0:SHL:24) ;- (CAN_MB)
AT91C_CAN_MOT_RX EQU (0x1:SHL:24) ;- (CAN_MB)
AT91C_CAN_MOT_RXOVERWRITE EQU (0x2:SHL:24) ;- (CAN_MB)
AT91C_CAN_MOT_TX EQU (0x3:SHL:24) ;- (CAN_MB)
AT91C_CAN_MOT_CONSUMER EQU (0x4:SHL:24) ;- (CAN_MB)
AT91C_CAN_MOT_PRODUCER EQU (0x5:SHL:24) ;- (CAN_MB)
;- -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register --------
AT91C_CAN_MIDvB EQU (0x3FFFF:SHL:0) ;- (CAN_MB) Complementary bits for identifier in extended mode
AT91C_CAN_MIDvA EQU (0x7FF:SHL:18) ;- (CAN_MB) Identifier for standard frame mode
AT91C_CAN_MIDE EQU (0x1:SHL:29) ;- (CAN_MB) Identifier Version
;- -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register --------
;- -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register --------
;- -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register --------
AT91C_CAN_MTIMESTAMP EQU (0xFFFF:SHL:0) ;- (CAN_MB) Timer Value
AT91C_CAN_MDLC EQU (0xF:SHL:16) ;- (CAN_MB) Mailbox Data Length Code
AT91C_CAN_MRTR EQU (0x1:SHL:20) ;- (CAN_MB) Mailbox Remote Transmission Request
AT91C_CAN_MABT EQU (0x1:SHL:22) ;- (CAN_MB) Mailbox Message Abort
AT91C_CAN_MRDY EQU (0x1:SHL:23) ;- (CAN_MB) Mailbox Ready
AT91C_CAN_MMI EQU (0x1:SHL:24) ;- (CAN_MB) Mailbox Message Ignored
;- -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register --------
;- -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register --------
;- -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register --------
AT91C_CAN_MACR EQU (0x1:SHL:22) ;- (CAN_MB) Abort Request for Mailbox
AT91C_CAN_MTCR EQU (0x1:SHL:23) ;- (CAN_MB) Mailbox Transfer Command
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Control Area Network Interface
;- *****************************************************************************
^ 0 ;- AT91S_CAN
CAN_MR # 4 ;- Mode Register
CAN_IER # 4 ;- Interrupt Enable Register
CAN_IDR # 4 ;- Interrupt Disable Register
CAN_IMR # 4 ;- Interrupt Mask Register
CAN_SR # 4 ;- Status Register
CAN_BR # 4 ;- Baudrate Register
CAN_TIM # 4 ;- Timer Register
CAN_TIMESTP # 4 ;- Time Stamp Register
CAN_ECR # 4 ;- Error Counter Register
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