at91sam7a3.rdf

ucosII 操作系统在at91sam7a3单片机上的实现。

# ========== Register definition for PMC peripheral ========== 
AT91C_PMC_IDR.name="AT91C_PMC_IDR"
AT91C_PMC_IDR.description="Interrupt Disable Register"
AT91C_PMC_IDR.helpkey="Interrupt Disable Register"
AT91C_PMC_IDR.access=memorymapped
AT91C_PMC_IDR.address=0xFFFFFC64
AT91C_PMC_IDR.width=32
AT91C_PMC_IDR.byteEndian=little
AT91C_PMC_IDR.type=enum
AT91C_PMC_IDR.enum.0.name=*** Write only ***
AT91C_PMC_IDR.enum.1.name=Error
AT91C_PMC_MOR.name="AT91C_PMC_MOR"
AT91C_PMC_MOR.description="Main Oscillator Register"
AT91C_PMC_MOR.helpkey="Main Oscillator Register"
AT91C_PMC_MOR.access=memorymapped
AT91C_PMC_MOR.address=0xFFFFFC20
AT91C_PMC_MOR.width=32
AT91C_PMC_MOR.byteEndian=little
AT91C_PMC_PLLR.name="AT91C_PMC_PLLR"
AT91C_PMC_PLLR.description="PLL Register"
AT91C_PMC_PLLR.helpkey="PLL Register"
AT91C_PMC_PLLR.access=memorymapped
AT91C_PMC_PLLR.address=0xFFFFFC2C
AT91C_PMC_PLLR.width=32
AT91C_PMC_PLLR.byteEndian=little
AT91C_PMC_PCER.name="AT91C_PMC_PCER"
AT91C_PMC_PCER.description="Peripheral Clock Enable Register"
AT91C_PMC_PCER.helpkey="Peripheral Clock Enable Register"
AT91C_PMC_PCER.access=memorymapped
AT91C_PMC_PCER.address=0xFFFFFC10
AT91C_PMC_PCER.width=32
AT91C_PMC_PCER.byteEndian=little
AT91C_PMC_PCER.type=enum
AT91C_PMC_PCER.enum.0.name=*** Write only ***
AT91C_PMC_PCER.enum.1.name=Error
AT91C_PMC_PCKR.name="AT91C_PMC_PCKR"
AT91C_PMC_PCKR.description="Programmable Clock Register"
AT91C_PMC_PCKR.helpkey="Programmable Clock Register"
AT91C_PMC_PCKR.access=memorymapped
AT91C_PMC_PCKR.address=0xFFFFFC40
AT91C_PMC_PCKR.width=32
AT91C_PMC_PCKR.byteEndian=little
AT91C_PMC_MCKR.name="AT91C_PMC_MCKR"
AT91C_PMC_MCKR.description="Master Clock Register"
AT91C_PMC_MCKR.helpkey="Master Clock Register"
AT91C_PMC_MCKR.access=memorymapped
AT91C_PMC_MCKR.address=0xFFFFFC30
AT91C_PMC_MCKR.width=32
AT91C_PMC_MCKR.byteEndian=little
AT91C_PMC_SCDR.name="AT91C_PMC_SCDR"
AT91C_PMC_SCDR.description="System Clock Disable Register"
AT91C_PMC_SCDR.helpkey="System Clock Disable Register"
AT91C_PMC_SCDR.access=memorymapped
AT91C_PMC_SCDR.address=0xFFFFFC04
AT91C_PMC_SCDR.width=32
AT91C_PMC_SCDR.byteEndian=little
AT91C_PMC_SCDR.type=enum
AT91C_PMC_SCDR.enum.0.name=*** Write only ***
AT91C_PMC_SCDR.enum.1.name=Error
AT91C_PMC_PCDR.name="AT91C_PMC_PCDR"
AT91C_PMC_PCDR.description="Peripheral Clock Disable Register"
AT91C_PMC_PCDR.helpkey="Peripheral Clock Disable Register"
AT91C_PMC_PCDR.access=memorymapped
AT91C_PMC_PCDR.address=0xFFFFFC14
AT91C_PMC_PCDR.width=32
AT91C_PMC_PCDR.byteEndian=little
AT91C_PMC_PCDR.type=enum
AT91C_PMC_PCDR.enum.0.name=*** Write only ***
AT91C_PMC_PCDR.enum.1.name=Error
AT91C_PMC_SCSR.name="AT91C_PMC_SCSR"
AT91C_PMC_SCSR.description="System Clock Status Register"
AT91C_PMC_SCSR.helpkey="System Clock Status Register"
AT91C_PMC_SCSR.access=memorymapped
AT91C_PMC_SCSR.address=0xFFFFFC08
AT91C_PMC_SCSR.width=32
AT91C_PMC_SCSR.byteEndian=little
AT91C_PMC_SCSR.permission.write=none
AT91C_PMC_PCSR.name="AT91C_PMC_PCSR"
AT91C_PMC_PCSR.description="Peripheral Clock Status Register"
AT91C_PMC_PCSR.helpkey="Peripheral Clock Status Register"
AT91C_PMC_PCSR.access=memorymapped
AT91C_PMC_PCSR.address=0xFFFFFC18
AT91C_PMC_PCSR.width=32
AT91C_PMC_PCSR.byteEndian=little
AT91C_PMC_PCSR.permission.write=none
AT91C_PMC_MCFR.name="AT91C_PMC_MCFR"
AT91C_PMC_MCFR.description="Main Clock  Frequency Register"
AT91C_PMC_MCFR.helpkey="Main Clock  Frequency Register"
AT91C_PMC_MCFR.access=memorymapped
AT91C_PMC_MCFR.address=0xFFFFFC24
AT91C_PMC_MCFR.width=32
AT91C_PMC_MCFR.byteEndian=little
AT91C_PMC_MCFR.permission.write=none
AT91C_PMC_SCER.name="AT91C_PMC_SCER"
AT91C_PMC_SCER.description="System Clock Enable Register"
AT91C_PMC_SCER.helpkey="System Clock Enable Register"
AT91C_PMC_SCER.access=memorymapped
AT91C_PMC_SCER.address=0xFFFFFC00
AT91C_PMC_SCER.width=32
AT91C_PMC_SCER.byteEndian=little
AT91C_PMC_SCER.type=enum
AT91C_PMC_SCER.enum.0.name=*** Write only ***
AT91C_PMC_SCER.enum.1.name=Error
AT91C_PMC_IMR.name="AT91C_PMC_IMR"
AT91C_PMC_IMR.description="Interrupt Mask Register"
AT91C_PMC_IMR.helpkey="Interrupt Mask Register"
AT91C_PMC_IMR.access=memorymapped
AT91C_PMC_IMR.address=0xFFFFFC6C
AT91C_PMC_IMR.width=32
AT91C_PMC_IMR.byteEndian=little
AT91C_PMC_IMR.permission.write=none
AT91C_PMC_IER.name="AT91C_PMC_IER"
AT91C_PMC_IER.description="Interrupt Enable Register"
AT91C_PMC_IER.helpkey="Interrupt Enable Register"
AT91C_PMC_IER.access=memorymapped
AT91C_PMC_IER.address=0xFFFFFC60
AT91C_PMC_IER.width=32
AT91C_PMC_IER.byteEndian=little
AT91C_PMC_IER.type=enum
AT91C_PMC_IER.enum.0.name=*** Write only ***
AT91C_PMC_IER.enum.1.name=Error
AT91C_PMC_SR.name="AT91C_PMC_SR"
AT91C_PMC_SR.description="Status Register"
AT91C_PMC_SR.helpkey="Status Register"
AT91C_PMC_SR.access=memorymapped
AT91C_PMC_SR.address=0xFFFFFC68
AT91C_PMC_SR.width=32
AT91C_PMC_SR.byteEndian=little
AT91C_PMC_SR.permission.write=none
# ========== Register definition for RSTC peripheral ========== 
AT91C_RSTC_RCR.name="AT91C_RSTC_RCR"
AT91C_RSTC_RCR.description="Reset Control Register"
AT91C_RSTC_RCR.helpkey="Reset Control Register"
AT91C_RSTC_RCR.access=memorymapped
AT91C_RSTC_RCR.address=0xFFFFFD00
AT91C_RSTC_RCR.width=32
AT91C_RSTC_RCR.byteEndian=little
AT91C_RSTC_RCR.type=enum
AT91C_RSTC_RCR.enum.0.name=*** Write only ***
AT91C_RSTC_RCR.enum.1.name=Error
AT91C_RSTC_RMR.name="AT91C_RSTC_RMR"
AT91C_RSTC_RMR.description="Reset Mode Register"
AT91C_RSTC_RMR.helpkey="Reset Mode Register"
AT91C_RSTC_RMR.access=memorymapped
AT91C_RSTC_RMR.address=0xFFFFFD08
AT91C_RSTC_RMR.width=32
AT91C_RSTC_RMR.byteEndian=little
AT91C_RSTC_RSR.name="AT91C_RSTC_RSR"
AT91C_RSTC_RSR.description="Reset Status Register"
AT91C_RSTC_RSR.helpkey="Reset Status Register"
AT91C_RSTC_RSR.access=memorymapped
AT91C_RSTC_RSR.address=0xFFFFFD04
AT91C_RSTC_RSR.width=32
AT91C_RSTC_RSR.byteEndian=little
AT91C_RSTC_RSR.permission.write=none
# ========== Register definition for SHDWC peripheral ========== 
AT91C_SHDWC_SHSR.name="AT91C_SHDWC_SHSR"
AT91C_SHDWC_SHSR.description="Shut Down Status Register"
AT91C_SHDWC_SHSR.helpkey="Shut Down Status Register"
AT91C_SHDWC_SHSR.access=memorymapped
AT91C_SHDWC_SHSR.address=0xFFFFFD18
AT91C_SHDWC_SHSR.width=32
AT91C_SHDWC_SHSR.byteEndian=little
AT91C_SHDWC_SHSR.permission.write=none
AT91C_SHDWC_SHMR.name="AT91C_SHDWC_SHMR"
AT91C_SHDWC_SHMR.description="Shut Down Mode Register"
AT91C_SHDWC_SHMR.helpkey="Shut Down Mode Register"
AT91C_SHDWC_SHMR.access=memorymapped
AT91C_SHDWC_SHMR.address=0xFFFFFD14
AT91C_SHDWC_SHMR.width=32
AT91C_SHDWC_SHMR.byteEndian=little
AT91C_SHDWC_SHCR.name="AT91C_SHDWC_SHCR"
AT91C_SHDWC_SHCR.description="Shut Down Control Register"
AT91C_SHDWC_SHCR.helpkey="Shut Down Control Register"
AT91C_SHDWC_SHCR.access=memorymapped
AT91C_SHDWC_SHCR.address=0xFFFFFD10
AT91C_SHDWC_SHCR.width=32
AT91C_SHDWC_SHCR.byteEndian=little
AT91C_SHDWC_SHCR.type=enum
AT91C_SHDWC_SHCR.enum.0.name=*** Write only ***
AT91C_SHDWC_SHCR.enum.1.name=Error
# ========== Register definition for RTTC peripheral ========== 
AT91C_RTTC_RTSR.name="AT91C_RTTC_RTSR"
AT91C_RTTC_RTSR.description="Real-time Status Register"
AT91C_RTTC_RTSR.helpkey="Real-time Status Register"
AT91C_RTTC_RTSR.access=memorymapped
AT91C_RTTC_RTSR.address=0xFFFFFD2C
AT91C_RTTC_RTSR.width=32
AT91C_RTTC_RTSR.byteEndian=little
AT91C_RTTC_RTSR.permission.write=none
AT91C_RTTC_RTMR.name="AT91C_RTTC_RTMR"
AT91C_RTTC_RTMR.description="Real-time Mode Register"
AT91C_RTTC_RTMR.helpkey="Real-time Mode Register"
AT91C_RTTC_RTMR.access=memorymapped
AT91C_RTTC_RTMR.address=0xFFFFFD20
AT91C_RTTC_RTMR.width=32
AT91C_RTTC_RTMR.byteEndian=little
AT91C_RTTC_RTVR.name="AT91C_RTTC_RTVR"
AT91C_RTTC_RTVR.description="Real-time Value Register"
AT91C_RTTC_RTVR.helpkey="Real-time Value Register"
AT91C_RTTC_RTVR.access=memorymapped
AT91C_RTTC_RTVR.address=0xFFFFFD28
AT91C_RTTC_RTVR.width=32
AT91C_RTTC_RTVR.byteEndian=little
AT91C_RTTC_RTVR.permission.write=none
AT91C_RTTC_RTAR.name="AT91C_RTTC_RTAR"
AT91C_RTTC_RTAR.description="Real-time Alarm Register"
AT91C_RTTC_RTAR.helpkey="Real-time Alarm Register"
AT91C_RTTC_RTAR.access=memorymapped
AT91C_RTTC_RTAR.address=0xFFFFFD24
AT91C_RTTC_RTAR.width=32
AT91C_RTTC_RTAR.byteEndian=little
# ========== Register definition for PITC peripheral ========== 
AT91C_PITC_PIVR.name="AT91C_PITC_PIVR"
AT91C_PITC_PIVR.description="Period Interval Value Register"
AT91C_PITC_PIVR.helpkey="Period Interval Value Register"
AT91C_PITC_PIVR.access=memorymapped
AT91C_PITC_PIVR.address=0xFFFFFD38
AT91C_PITC_PIVR.width=32
AT91C_PITC_PIVR.byteEndian=little
AT91C_PITC_PIVR.permission.write=none
AT91C_PITC_PISR.name="AT91C_PITC_PISR"
AT91C_PITC_PISR.description="Period Interval Status Register"
AT91C_PITC_PISR.helpkey="Period Interval Status Register"
AT91C_PITC_PISR.access=memorymapped
AT91C_PITC_PISR.address=0xFFFFFD34
AT91C_PITC_PISR.width=32
AT91C_PITC_PISR.byteEndian=little
AT91C_PITC_PISR.permission.write=none
AT91C_PITC_PIIR.name="AT91C_PITC_PIIR"
AT91C_PITC_PIIR.description="Period Interval Image Register"
AT91C_PITC_PIIR.helpkey="Period Interval Image Register"
AT91C_PITC_PIIR.access=memorymapped
AT91C_PITC_PIIR.address=0xFFFFFD3C
AT91C_PITC_PIIR.width=32
AT91C_PITC_PIIR.byteEndian=little
AT91C_PITC_PIIR.permission.write=none
AT91C_PITC_PIMR.name="AT91C_PITC_PIMR"
AT91C_PITC_PIMR.description="Period Interval Mode Register"
AT91C_PITC_PIMR.helpkey="Period Interval Mode Register"
AT91C_PITC_PIMR.access=memorymapped
AT91C_PITC_PIMR.address=0xFFFFFD30
AT91C_PITC_PIMR.width=32
AT91C_PITC_PIMR.byteEndian=little
# ========== Register definition for WDTC peripheral ========== 
AT91C_WDTC_WDCR.name="AT91C_WDTC_WDCR"
AT91C_WDTC_WDCR.description="Watchdog Control Register"
AT91C_WDTC_WDCR.helpkey="Watchdog Control Register"
AT91C_WDTC_WDCR.access=memorymapped
AT91C_WDTC_WDCR.address=0xFFFFFD40
AT91C_WDTC_WDCR.width=32
AT91C_WDTC_WDCR.byteEndian=little
AT91C_WDTC_WDCR.type=enum
AT91C_WDTC_WDCR.enum.0.name=*** Write only ***
AT91C_WDTC_WDCR.enum.1.name=Error
AT91C_WDTC_WDSR.name="AT91C_WDTC_WDSR"
AT91C_WDTC_WDSR.description="Watchdog Status Register"
AT91C_WDTC_WDSR.helpkey="Watchdog Status Register"
AT91C_WDTC_WDSR.access=memorymapped
AT91C_WDTC_WDSR.address=0xFFFFFD48
AT91C_WDTC_WDSR.width=32
AT91C_WDTC_WDSR.byteEndian=little
AT91C_WDTC_WDSR.permission.write=none
AT91C_WDTC_WDMR.name="AT91C_WDTC_WDMR"
AT91C_WDTC_WDMR.description="Watchdog Mode Register"
AT91C_WDTC_WDMR.helpkey="Watchdog Mode Register"
AT91C_WDTC_WDMR.access=memorymapped
AT91C_WDTC_WDMR.address=0xFFFFFD44
AT91C_WDTC_WDMR.width=32
AT91C_WDTC_WDMR.byteEndian=little
# ========== Register definition for MC peripheral ========== 
AT91C_MC_PUIA.name="AT91C_MC_PUIA"
AT91C_MC_PUIA.description="MC Protection Unit Area"
AT91C_MC_PUIA.helpkey="MC Protection Unit Area"
AT91C_MC_PUIA.access=memorymapped
AT91C_MC_PUIA.address=0xFFFFFF10
AT91C_MC_PUIA.width=32
AT91C_MC_PUIA.byteEndian=little
AT91C_MC_FMR.name="AT91C_MC_FMR"
AT91C_MC_FMR.description="MC Flash Mode Register"
AT91C_MC_FMR.helpkey="MC Flash Mode Register"
AT91C_MC_FMR.access=memorymapped
AT91C_MC_FMR.address=0xFFFFFF60
AT91C_MC_FMR.width=32
AT91C_MC_FMR.byteEndian=little
AT91C_MC_RCR.name="AT91C_MC_RCR"
AT91C_MC_RCR.description="MC Remap Control Register"
AT91C_MC_RCR.helpkey="MC Remap Control Register"
AT91C_MC_RCR.access=memorymapped
AT91C_MC_RCR.address=0xFFFFFF00
AT91C_MC_RCR.width=32
AT91C_MC_RCR.byteEndian=little
AT91C_MC_RCR.type=enum
AT91C_MC_RCR.enum.0.name=*** Write only ***
AT91C_MC_RCR.enum.1.name=Error
AT91C_MC_ASR.name="AT91C_MC_ASR"
AT91C_MC_ASR.description="MC Abort Status Register"
AT91C_MC_ASR.helpkey="MC Abort Status Register"
AT91C_MC_ASR.access=memorymapped
AT91C_MC_ASR.address=0xFFFFFF04
AT91C_MC_ASR.width=32
AT91C_MC_ASR.byteEndian=little
AT91C_MC_ASR.permission.write=none
AT91C_MC_PUP.name="AT91C_MC_PUP"
AT91C_MC_PUP.description="MC Protection Unit Peripherals"
AT91C_MC_PUP.helpkey="MC Protection Unit Peripherals"
AT91C_MC_PUP.access=memorymapped
AT91C_MC_PUP.address=0xFFFFFF50
AT91C_MC_PUP.width=32
AT91C_MC_PUP.byteEndian=little
AT91C_MC_AASR.name="AT91C_MC_AASR"
AT91C_MC_AASR.description="MC Abort Address Status Register"
AT91C_MC_AASR.helpkey="MC Abort Address Status Register"
AT91C_MC_AASR.access=memorymapped
AT91C_MC_AASR.address=0xFFFFFF08
AT91C_MC_AASR.width=32
AT91C_MC_AASR.byteEndian=little
AT91C_MC_AASR.permission.write=none
AT91C_MC_FCR.name="AT91C_MC_FCR"