ext_sdram.ini

lpc3250 example program

/******************************************************************************/
/* Ext_SDRAM.ini: External SDRAM Initialization File                          */
/******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>>                           // 
/******************************************************************************/
/* This file is part of the uVision/ARM development tools.                    */
/* Copyright (c) 2005-2008 Keil Software. All rights reserved.                */
/* This software may only be used under the terms of a valid, current,        */
/* end user licence from KEIL for a compatible version of KEIL software       */
/* development tools. Nothing else gives you the right to use this software.  */
/******************************************************************************/


DEFINE CHAR Setup;
DEFINE INT  Entry;

// Memory mapped peripherals address definitions
DEFINE LONG SYS;
DEFINE LONG EMC;
SYS    = 0x40004000;
EMC    = 0x31080000;


FUNC void Clock_Setup (void) {
  if (Setup & 0x01) {
    // Setup clock: XTAL                      =  13.00 MHz, 
    //              SYSCLK                    =  13.00 MHz, 
    //              HCLKPLL                   = 208.00 MHz, 
    //              ARM_CLK    = HCLKPLL      = 208.00 MHz
    //              HCLK       = HCLKPLL / 2  = 104.00 MHz
    //              PERIPH_CLK = HCLKPLL / 16 =  13.00 MHz
    LONG PWR_CTRL, OSC_CTRL, SYSCLK_CTRL, PLL397_CTRL, HCLKPLL_CTRL, HCLKDIV_CTRL; 

    PWR_CTRL        = SYS + 0x44;       // Power Control Register  Address
    OSC_CTRL        = SYS + 0x4C;       // Main Oscilator Ctrl Reg Address
    SYSCLK_CTRL     = SYS + 0x50;       // SYSCLK Control Register Address
    PLL397_CTRL     = SYS + 0x48;       // PLL397 Control Register Address
    HCLKPLL_CTRL    = SYS + 0x58;       // ARM and HCLK Ctrl Reg   Address
    HCLKDIV_CTRL    = SYS + 0x40;       // HCLK Divider Settings   Address

    _sleep_ (10);
    _WDWORD(SYSCLK_CTRL  , 0x00000140);
    _WDWORD(OSC_CTRL     , 0x00000000);
    _WDWORD(HCLKPLL_CTRL , 0x0001401E);
    _sleep_ (10);
    _WDWORD(HCLKDIV_CTRL , 0x0000003D);
    _WDWORD(PWR_CTRL     , 0x00000016);
  }
}

FUNC void EMC_Setup (void) {
  // External Memory Controller (EMC) User Interface
  if (Setup & 0x02) {

  LONG EMCControl, EMCStatus, EMCConfig, EMCDynControl, EMCDynRefresh, 
       EMCDynReadCfg, EMCDynRP, EMCDynRAS, EMCDynSREX, EMCDynWR,
       EMCDynRC, EMCDynRFC, EMCDynXSR, EMCDynRRD, EMCDynMRD, EMCDynCDLR, 
       EMCStaExtWait, EMCDynConfig0,  EMCDynRasCas0, EMCDynConfig1, 
       EMCDynRasCas1, 
       EMCStaConfig0, EMCStaWaitWen0, EMCStaWaitOen0, EMCStaWaitRd0, 
       EMCStaWaitPage0, EMCStaWaitWr0, EMCStaWaitTurn0,
       EMCStaConfig1, EMCStaWaitWen1, EMCStaWaitOen1, EMCStaWaitRd1, 
       EMCStaWaitPage1, EMCStaWaitWr1, EMCStaWaitTurn1,
       EMCStaConfig2, EMCStaWaitWen2, EMCStaWaitOen2, EMCStaWaitRd2, 
       EMCStaWaitPage2, EMCStaWaitWr2, EMCStaWaitTurn2,
       EMCStaConfig3, EMCStaWaitWen3, EMCStaWaitOen3, EMCStaWaitRd3, 
       EMCStaWaitPage3, EMCStaWaitWr3, EMCStaWaitTurn3,
       EMCAHBControl0, EMCAHBStatus0, EMCAHBTimeOut0,
       EMCAHBControl2, EMCAHBStatus2, EMCAHBTimeOut2,
       EMCAHBControl3, EMCAHBStatus3, EMCAHBTimeOut3,
       EMCAHBControl4, EMCAHBStatus4, EMCAHBTimeOut4;
  LONG SDRAMCLK_CTRL;
  LONG SDRAM_MODE_REG, SDRAM_EXT_MODE_REG;
  LONG NORMAL_CMD, MODE_CMD, PALL_CMD, NOP_CMD, REFSH_MODE;

    SDRAMCLK_CTRL       = SYS + 0x068;  // SDRAM Clock Control Reg Address
    EMCControl          = EMC + 0x000;  // Memory Controller Contr Address
    EMCStatus           = EMC + 0x004;  // EMC Status              Address
    EMCConfig           = EMC + 0x008;  // Mem Controller Oper Cfg Address
    EMCDynControl       = EMC + 0x020;  // Dynamic Mem Control Reg Address
    EMCDynRefresh       = EMC + 0x024;  // Dynamic Mem Refresh Reg Address
    EMCDynReadCfg       = EMC + 0x028;  // Dynamic Mem Read Config Address
    EMCDynRP            = EMC + 0x030;  // Precharge Cmd Period    Address
    EMCDynRAS           = EMC + 0x034;  // Active to Prchg Period  Address
    EMCDynSREX          = EMC + 0x038;  // Self-refresh Exit Time  Address
    EMCDynWR            = EMC + 0x044;  // Write Recovery Time     Address
    EMCDynRC            = EMC + 0x048;  // Act to Act Cmd Period   Address
    EMCDynRFC           = EMC + 0x04C;  // Auto-refresh Period     Address
    EMCDynXSR           = EMC + 0x050;  // Exit Selfref to Act Cmd Address
    EMCDynRRD           = EMC + 0x054;  // Active bank A to B      Address
    EMCDynMRD           = EMC + 0x058;  // Load Mode to Act Cmd    Address
    EMCDynCDLR          = EMC + 0x05C;  // Last data into Read Cmd Address
    EMCStaExtWait       = EMC + 0x080;  // Static Mem Extend Wait  Address
    EMCDynConfig0       = EMC + 0x100;  // SDRAM0 Config Info      Address
    EMCDynRasCas0       = EMC + 0x104;  // RAS0 and CAS0 Latencies Address
    EMCDynConfig1       = EMC + 0x120;  // SDRAM1 Config Info      Address
    EMCDynRasCas1       = EMC + 0x124;  // RAS1 and CAS1 Latencies Address
    EMCStaConfig0       = EMC + 0x200;  // CS0 Memory Config       Address
    EMCStaWaitWen0      = EMC + 0x204;  // CS0 to Wr Enable Delay  Address
    EMCStaWaitOen0      = EMC + 0x208;  // CS0 to Out Enable Delay Address
    EMCStaWaitRd0       = EMC + 0x20C;  // CS0 to Rd Access Delay  Address
    EMCStaWaitPage0     = EMC + 0x210;  // CS0 Seq Access Delay    Address
    EMCStaWaitWr0       = EMC + 0x214;  // CS0 to Wr Access Delay  Address
    EMCStaWaitTurn0     = EMC + 0x218;  // CS0 Turnaround Cycles   Address
    EMCStaConfig1       = EMC + 0x220;  // CS1 Memory Config       Address
    EMCStaWaitWen1      = EMC + 0x224;  // CS1 to Wr Enable Delay  Address
    EMCStaWaitOen1      = EMC + 0x228;  // CS1 to Out Enable Delay Address
    EMCStaWaitRd1       = EMC + 0x22C;  // CS1 to Rd Access Delay  Address
    EMCStaWaitPage1     = EMC + 0x230;  // CS1 Seq Access Delay    Address
    EMCStaWaitWr1       = EMC + 0x234;  // CS1 to Wr Access Delay  Address
    EMCStaWaitTurn1     = EMC + 0x238;  // CS1 Turnaround Cycles   Address
    EMCStaConfig2       = EMC + 0x240;  // CS2 Memory Config       Address
    EMCStaWaitWen2      = EMC + 0x244;  // CS2 to Wr Enable Delay  Address
    EMCStaWaitOen2      = EMC + 0x248;  // CS2 to Out Enable Delay Address
    EMCStaWaitRd2       = EMC + 0x24C;  // CS2 to Rd Access Delay  Address
    EMCStaWaitPage2     = EMC + 0x250;  // CS2 Seq Access Delay    Address
    EMCStaWaitWr2       = EMC + 0x254;  // CS2 to Wr Access Delay  Address
    EMCStaWaitTurn2     = EMC + 0x258;  // CS2 Turnaround Cycles   Address
    EMCStaConfig3       = EMC + 0x260;  // CS3 Memory Config       Address
    EMCStaWaitWen3      = EMC + 0x264;  // CS3 to Wr Enable Delay  Address
    EMCStaWaitOen3      = EMC + 0x268;  // CS3 to Out Enable Delay Address
    EMCStaWaitRd3       = EMC + 0x26C;  // CS3 to Rd Access Delay  Address
    EMCStaWaitPage3     = EMC + 0x270;  // CS3 Seq Access Delay    Address
    EMCStaWaitWr3       = EMC + 0x274;  // CS3 to Wr Access Delay  Address
    EMCStaWaitTurn3     = EMC + 0x278;  // CS3 Turnaround Cycles   Address
    EMCAHBControl0      = EMC + 0x400;  // AHB port 0 Control Reg  Address
    EMCAHBStatus0       = EMC + 0x404;  // AHB port 0 Status  Reg  Address
    EMCAHBTimeOut0      = EMC + 0x408;  // AHB port 0 Timeout Reg  Address
    EMCAHBControl2      = EMC + 0x440;  // AHB port 2 Control Reg  Address
    EMCAHBStatus2       = EMC + 0x444;  // AHB port 2 Status  Reg  Address
    EMCAHBTimeOut2      = EMC + 0x448;  // AHB port 2 Timeout Reg  Address
    EMCAHBControl3      = EMC + 0x460;  // AHB port 3 Control Reg  Address
    EMCAHBStatus3       = EMC + 0x464;  // AHB port 3 Status  Reg  Address
    EMCAHBTimeOut3      = EMC + 0x468;  // AHB port 3 Timeout Reg  Address
    EMCAHBControl4      = EMC + 0x480;  // AHB port 4 Control Reg  Address
    EMCAHBStatus4       = EMC + 0x484;  // AHB port 4 Status  Reg  Address
    EMCAHBTimeOut4      = EMC + 0x488;  // AHB port 4 Timeout Reg  Address

    SDRAM_MODE_REG      = 0x80018000;   // SDRAM Mode Register     Address
    SDRAM_EXT_MODE_REG  = 0x8102C000;   // SDRAM Extended Mode Reg Address

    // Constants
    NORMAL_CMD          = (0x0 << 7);   // NORMAL        Command
    MODE_CMD            = (0x1 << 7);   // MODE          Command
    PALL_CMD            = (0x2 << 7);   // Precharge All Command
    NOP_CMD             = (0x3 << 7);   // NOP           Command
    REFSH_MODE          = (0x1 << 2);   // Self-refresh mode

    // Setup EMC Controller
    _WDWORD(EMCControl     , 0x00000001);
    _WDWORD(EMCConfig      , 0x00000000);

    if (Setup & 0x04) {
      //  Setup Dynamic Memory Interface
      // Initialize Dynamic Memory Controller to interface
      _WDWORD(SDRAMCLK_CTRL  , 0x0001C000);

      // 64 MB of SDRAM connected on DYCS0
      _WDWORD(EMCDynRP       , 0x00000001);
      _WDWORD(EMCDynRAS      , 0x00000004);
      _WDWORD(EMCDynSREX     , 0x00000008);
      _WDWORD(EMCDynWR       , 0x00000001);
      _WDWORD(EMCDynRC       , 0x00000007);
      _WDWORD(EMCDynRFC      , 0x00000008);
      _WDWORD(EMCDynXSR      , 0x00000008);
      _WDWORD(EMCDynRRD      , 0x00000002);
      _WDWORD(EMCDynMRD      , 0x00000002);
      _WDWORD(EMCDynCDLR     , 0x00000001);
      _WDWORD(EMCDynReadCfg  , 0x00000011);
      _WDWORD(EMCDynRasCas0  , 0x00000302);
      _WDWORD(EMCDynConfig0  , 0x00005682);
      _WDWORD(EMCDynControl  , NOP_CMD   |0x03);
      _sleep_ (1);
      _WDWORD(EMCDynControl  , PALL_CMD  |0x03);
      _WDWORD(EMCDynControl  , NOP_CMD   |0x03);
      _WDWORD(EMCDynRefresh  , 0x00000002);
      _sleep_ (1);
      _WDWORD(EMCDynRefresh  , 0x00000032);
      _sleep_ (1);
      _WDWORD(EMCDynControl  , MODE_CMD  |0x03);
      _RDWORD(SDRAM_MODE_REG);
      _sleep_ (1);
      _RDWORD(SDRAM_EXT_MODE_REG);
      _WDWORD(EMCDynControl  , NORMAL_CMD|0x03);
      _sleep_ (1);
      _WDWORD(EMCAHBControl0 , 0x00000001);
      _WDWORD(EMCAHBTimeOut0 , 0x00000064);
      _WDWORD(EMCAHBControl2 , 0x00000001);
      _WDWORD(EMCAHBTimeOut2 , 0x00000190);
      _WDWORD(EMCAHBControl3 , 0x00000001);
      _WDWORD(EMCAHBTimeOut3 , 0x00000190);
      _WDWORD(EMCAHBControl4 , 0x00000001);
      _WDWORD(EMCAHBTimeOut4 , 0x00000190);
    }

    if (Setup & 0x08) {
      //  Setup Static Memory Interface
      // Setup controller for External NOR Flash 
      _WDWORD(EMCStaConfig0  , 0x00000081);
      _WDWORD(EMCStaWaitWen0 , 0x00000000);
      _WDWORD(EMCStaWaitOen0 , 0x00000000);
      _WDWORD(EMCStaWaitRd0  , 0x00000007);
      _WDWORD(EMCStaWaitPage0, 0x00000000);
      _WDWORD(EMCStaWaitWr0  , 0x00000000);
      _WDWORD(EMCStaWaitTurn0, 0x00000000);
      _WDWORD(EMCStaExtWait  , 0x00000000);
    }
  }
}

FUNC void Remap (void) {
  if (Setup & 0x10) {
    LONG BOOT_MAP;
    BOOT_MAP = SYS + 0x14;              // Boot Map Control        Address
    _WDWORD(BOOT_MAP, 0x00000001);      // Remap IRAM to 0
  }
}

FUNC void PC_Setup (void) {
  if (Setup & 0x40) {
    PC = Entry;
  }
}

FUNC void GoMain (void) {
  if ((Setup & 0xA0) == 0xA0) {
    exec("g,main");
  }
}


// <o1.0> Clock Setup
// <e1.1> EMC Setup
//   <o1.2> Dynamic Memory Setup
//   <o1.3> Static Memory Setup
// </e>
// <e1.4> Remap
// </e>
// <e1.5> Download Program
FUNC void Download (void) {
  if (Setup & 0x20) {
//  <s0.80> Command for Loading
    exec("LOAD Ext_SDRAM\\Blinky.axf INCREMENTAL");
  }
}
// </e>
// <e0.6> Setup Program Counter to Entry Point
//   <o1> Program Entry Point <0x0-0xFFFFFFFF>
// </e>
// <e.7> Execute Program untill Main Function
// </e>
Setup = 0xE7;
Entry = 0x80000000;


Clock_Setup();
EMC_Setup();
Remap();
Download();
PC_Setup();
GoMain();