bs_decoding.v

a H.264/AVC Baseline Decoder

				4'd10:mbAddrB_coeff_reg[43:40] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
			endcase
	//-------------------------------------------------
	//backup mbAddrA coding information to derive bs_V0
	//-------------------------------------------------
	reg [3:0] mbAddrA_coeff;
	reg [31:0] mbAddrA_mvx;
	reg [31:0] mbAddrA_mvy;
	always @ (posedge clk)
		if (reset_n == 1'b0)
			begin
				mbAddrA_coeff <= 4'b0;
				mbAddrA_mvx	 <= 32'b0;
				mbAddrA_mvy  <= 32'b0;
			end
		else if (!disable_DF && mb_num_h != 0 && 
			((mb_type_general == `MB_P_skip && Is_skipMB_mv_calc && MBTypeGen_mbAddrA[1] == 1'b0) //Current MB is P_skip 
			|| (slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0)))				//Current MB is Inter
			begin
				mbAddrA_mvx <= mvx_mbAddrA;	mbAddrA_mvy <= mvy_mbAddrA;
				//if mbAddrA is Inter (not P_skip),back up non-zero residual coeff information
				if (MBTypeGen_mbAddrA[0] == 1'b0)	mbAddrA_coeff <= {currMB_coeff[15],currMB_coeff[13],currMB_coeff[7],currMB_coeff[5]};
			end
	//-------------------------------------------------
	//backup mbAddrB coding information to derive bs_H0
	//-------------------------------------------------
	
	//1)For P_skip,at "Is_skipMB_mv_calc", no matter DF is enabled or not,mvx_mbAddrB/mvy_mbAddrB should be read to 
	//	derive current motion vector
	//2)For Inter other than P_skip, mvx_mbAddrB/mvy_mbAddrB are read at mb_pred or sub_mb_pred state.So we add a new
	//	signal "mv_mbAddrB_rd_for_DF" at "slice_data_state == `mb_type_s"
	assign mv_mbAddrB_rd_for_DF = (!disable_DF && slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0 && mb_num_v != 0);
	reg [3:0] mbAddrB_coeff;
	reg [31:0] mbAddrB_mvx;
	reg [31:0] mbAddrB_mvy;
	always @ (posedge clk)
		if (reset_n == 1'b0)
			begin
				mbAddrB_coeff <= 4'b0;
				mbAddrB_mvx	 <= 32'b0;
				mbAddrB_mvy  <= 32'b0;
			end
		else if (!disable_DF && mb_num_v != 0 && 
			((mb_type_general == `MB_P_skip && Is_skipMB_mv_calc && MBTypeGen_mbAddrB[1] == 1'b0)	//Current MB is P_skip 
			|| (slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0)))				//Current MB is Inter
			begin
				mbAddrB_mvx <= mvx_mbAddrB_dout;	mbAddrB_mvy <= mvy_mbAddrB_dout;
				//if mbAddrB is Inter (not P_skip),back up non-zero residual coeff information
				if (MBTypeGen_mbAddrB[0] == 1'b0)
					case (mb_num_h)
						4'd0 :mbAddrB_coeff <= mbAddrB_coeff_reg[3:0];
						4'd1 :mbAddrB_coeff <= mbAddrB_coeff_reg[7:4];
						4'd2 :mbAddrB_coeff <= mbAddrB_coeff_reg[11:8];
						4'd3 :mbAddrB_coeff <= mbAddrB_coeff_reg[15:12];
						4'd4 :mbAddrB_coeff <= mbAddrB_coeff_reg[19:16];
						4'd5 :mbAddrB_coeff <= mbAddrB_coeff_reg[23:20];
						4'd6 :mbAddrB_coeff <= mbAddrB_coeff_reg[27:24];
						4'd7 :mbAddrB_coeff <= mbAddrB_coeff_reg[31:28];
						4'd8 :mbAddrB_coeff <= mbAddrB_coeff_reg[35:32];
						4'd9 :mbAddrB_coeff <= mbAddrB_coeff_reg[39:36];
						4'd10:mbAddrB_coeff <= mbAddrB_coeff_reg[43:40];
					endcase
			end
	
	always @ (posedge gclk_bs_dec or negedge reset_n)
		if (reset_n == 1'b0)
			begin
				bs_V0 <= 0;	bs_V1 <= 0;	bs_V2 <= 0;	bs_V3 <= 0;
				bs_H0 <= 0;	bs_H1 <= 0;	bs_H2 <= 0;	bs_H3 <= 0;
			end
		//-----------------------
		//Current MB is P_skip
		//-----------------------
		else if (mb_type_general_DF == `MB_P_skip)
			case (bs_dec_counter)
				2'b00:
				begin
					//V0
					if (mb_num_h == 0) 						//edge of frame,bs = 0
						bs_V0 <= 12'b0;
					else if (MBTypeGen_mbAddrA[1] == 1'b1) 	//mbAddrA is Intra,bs = 4
						bs_V0 <= 12'b100100100100;
					else if (MBTypeGen_mbAddrA    == `MB_addrA_addrB_P_skip)	//mbAddrA is P_skip
						bs_V0 <= (mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 12'b001001001001:12'b0;
					else 									//mbAddrA is Inter
						begin 
							bs_V0[2:0]  <= (mbAddrA_coeff[0])? 3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
							bs_V0[5:3]  <= (mbAddrA_coeff[1])? 3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;	
							bs_V0[8:6]  <= (mbAddrA_coeff[2])? 3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;	
							bs_V0[11:9] <= (mbAddrA_coeff[3])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;	
						end
					//H0
					if (mb_num_v == 0)						//edge of frame,bs = 0
						bs_H0 <= 12'b0;
					else if (MBTypeGen_mbAddrB[1] == 1'b1)	//mbAddrB is Intra,bs=4
						bs_H0 <= 12'b100100100100;
					else if (MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip)	//mbAddrB is P_skip
						bs_H0 <= (mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 12'b001001001001:12'b0;
					else
						begin 
							bs_H0[2:0]  <= (mbAddrB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
							bs_H0[5:3]  <= (mbAddrB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;	
							bs_H0[8:6]  <= (mbAddrB_coeff[2])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;	
							bs_H0[11:9] <= (mbAddrB_coeff[3])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;	
						end
				end
				2'b11:begin	bs_V1 <= 0;	bs_H1 <= 0;	end
				2'b10:begin	bs_V2 <= 0;	bs_H2 <= 0;	end
				2'b01:begin	bs_V3 <= 0;	bs_H3 <= 0;	end
			endcase
			//--------------------
			//Current MB is Intra
			//-----------------------
			else if (mb_type_general_DF[3] == 1'b1)
				case (bs_dec_counter)
					2'b00:
					begin
						bs_V0 <= (mb_num_h == 0)? 12'b0:12'b100100100100; 
						bs_H0 <= (mb_num_v == 0)? 12'b0:12'b100100100100;
					end
					2'b11:begin bs_V1 <= 12'b011011011011;	bs_H1 <= 12'b011011011011; end 
					2'b10:begin bs_V2 <= 12'b011011011011;	bs_H2 <= 12'b011011011011; end 
					2'b01:begin	bs_V3 <= 12'b011011011011; 	bs_H3 <= 12'b011011011011; end
				endcase
			//-----------------------
			//Current MB is Inter
			//-----------------------
			else 
				case (bs_dec_counter)
					2'b00:	//V0,H0
					begin
						//V0
						if (mb_num_h == 0) 						//edge of frame,bs = 0
							bs_V0 <= 12'b0;
						else if (MBTypeGen_mbAddrA[1] == 1'b1) 	//mbAddrA is Intra,bs = 4
							bs_V0 <= 12'b100100100100;
						else if (MBTypeGen_mbAddrA    == `MB_addrA_addrB_P_skip)	//mbAddrA is P_skip
							begin
								bs_V0[2:0]  <= (currMB_coeff[0])?  3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
								bs_V0[5:3]  <= (currMB_coeff[2])?  3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
								bs_V0[8:6]  <= (currMB_coeff[8])?  3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
								bs_V0[11:9] <= (currMB_coeff[10])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
							end
						else 									//mbAddrA is Inter
							begin 
								bs_V0[2:0]  <= (mbAddrA_coeff[0] || currMB_coeff[0])?  3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
								bs_V0[5:3]  <= (mbAddrA_coeff[1] || currMB_coeff[2])?  3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;	
								bs_V0[8:6]  <= (mbAddrA_coeff[2] || currMB_coeff[8])?  3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;	
								bs_V0[11:9] <= (mbAddrA_coeff[3] || currMB_coeff[10])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;	
							end
						//H0
						if (mb_num_v == 0) 						//edge of frame,bs = 0
							bs_H0 <= 12'b0;
						else if (MBTypeGen_mbAddrB[1] == 1'b1) 	//mbAddrB is Intra,bs = 4
							bs_H0 <= 12'b100100100100;
						else if (MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip)	//mbAddrB is P_skip
							begin
								bs_H0[2:0]  <= (currMB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
								bs_H0[5:3]  <= (currMB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
								bs_H0[8:6]  <= (currMB_coeff[4])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
								bs_H0[11:9] <= (currMB_coeff[5])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
							end
						else 										//mbAddrB is Inter
							begin 
								bs_H0[2:0]  <= (mbAddrB_coeff[0] || currMB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
								bs_H0[5:3]  <= (mbAddrB_coeff[1] || currMB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;	
								bs_H0[8:6]  <= (mbAddrB_coeff[2] || currMB_coeff[4])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;	
								bs_H0[11:9] <= (mbAddrB_coeff[3] || currMB_coeff[5])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;	
							end
					end
					2'b11://V1,H1
					begin
						bs_V1[2:0]  <= (currMB_coeff[0]  || currMB_coeff[1])?  3'd2:(MB_inter_size != `I8x8)? 
										0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;	  
						
						bs_V1[5:3]  <= (currMB_coeff[2]  || currMB_coeff[3])?  3'd2:(MB_inter_size != `I8x8)?
										0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;	
						
						bs_V1[8:6]  <= (currMB_coeff[8]  || currMB_coeff[9])?  3'd2:(MB_inter_size != `I8x8)?
										0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
						
						bs_V1[11:9] <= (currMB_coeff[10] || currMB_coeff[11])? 3'd2:(MB_inter_size != `I8x8)?
										0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
						
						bs_H1[2:0]  <= (currMB_coeff[0]  || currMB_coeff[2])?  3'd2:(MB_inter_size != `I8x8)?
										0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
						
						bs_H1[5:3]  <= (currMB_coeff[1]  || currMB_coeff[3])?  3'd2:(MB_inter_size != `I8x8)?
										0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
						
						bs_H1[8:6]  <= (currMB_coeff[4]  || currMB_coeff[6])?  3'd2:(MB_inter_size != `I8x8)?
										0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;					
						bs_H1[11:9] <= (currMB_coeff[5]  || currMB_coeff[7])?  3'd2:(MB_inter_size != `I8x8)?
										0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
					end
					2'b10://V2,H2
					begin
						bs_V2[2:0]  <= (currMB_coeff[1]  || currMB_coeff[4])?  3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
										0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;	
										
						bs_V2[5:3]  <= (currMB_coeff[3]  || currMB_coeff[6])?  3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
										0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;	 
										
						bs_V2[8:6]  <= (currMB_coeff[9]  || currMB_coeff[12])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
										0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;	
										
						bs_V2[11:9] <= (currMB_coeff[11] || currMB_coeff[14])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
										0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;	
										
						bs_H2[2:0]  <= (currMB_coeff[2]  || currMB_coeff[8])?  3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
										0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;	
										
						bs_H2[5:3]  <= (currMB_coeff[3]  || currMB_coeff[9])?  3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
										0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
										
						bs_H2[8:6]  <= (currMB_coeff[6]  || currMB_coeff[12])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
										0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;					
										
						bs_H2[11:9] <= (currMB_coeff[7]  || currMB_coeff[13])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
										0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
					end
					2'b01://V3,H3
					begin
						bs_V3[2:0]  <= (currMB_coeff[4]  || currMB_coeff[5])?  3'd2:(MB_inter_size != `I8x8)?
										0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
						
						bs_V3[5:3]  <= (currMB_coeff[6]  || currMB_coeff[7])?  3'd2:(MB_inter_size != `I8x8)?