bs_decoding.v

a H.264/AVC Baseline Decoder

//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : [e-mail]
// File      : bs_decoding.v
// Generated : Nov 17,2005
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Deblocking Filter Boundary Strength decoding
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module bs_decoding (clk,reset_n,gclk_bs_dec,gclk_end_of_MB_DEC,end_of_MB_DEC,end_of_one_blk4x4_sum,mb_num_h,mb_num_v,
	disable_DF,blk4x4_rec_counter,CodedBlockPatternLuma,mb_type_general,slice_data_state,residual_state,
	MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,end_of_one_residual_block,TotalCoeff,
	curr_DC_IsZero,Is_skipMB_mv_calc,
	mvx_mbAddrA,mvy_mbAddrA,mvx_mbAddrB_dout,mvy_mbAddrB_dout,
	mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,
	
	bs_dec_counter,end_of_BS_DEC,mv_mbAddrB_rd_for_DF,
	bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3
	);
	input clk;
	input reset_n;
	input gclk_bs_dec;
	input gclk_end_of_MB_DEC;
	input end_of_MB_DEC;
	input end_of_one_blk4x4_sum;
	input [3:0] mb_num_h;
	input [3:0] mb_num_v;
	input [4:0] blk4x4_rec_counter;
	input disable_DF;
	input [3:0] CodedBlockPatternLuma;
	input [3:0] mb_type_general;
	input [3:0] slice_data_state;
	input [3:0] residual_state;
	input [1:0]  MBTypeGen_mbAddrA;
	input [21:0] MBTypeGen_mbAddrB_reg;
	input end_of_one_residual_block;
	input [4:0] TotalCoeff;
	input curr_DC_IsZero;
	input Is_skipMB_mv_calc;
	input [31:0] mvx_mbAddrA,mvy_mbAddrA,mvx_mbAddrB_dout,mvy_mbAddrB_dout;
	input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
	input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
	
	output [1:0] bs_dec_counter;
	output end_of_BS_DEC;
	output mv_mbAddrB_rd_for_DF;
	output [11:0] bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3;
	
	reg [11:0] bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3;
		
	//-------------------------------------------
	//mb_type_general needs to be latched for DF
	//-------------------------------------------
	reg [3:0] mb_type_general_DF;
	always @ (posedge clk)
		if (reset_n == 1'b0)
			mb_type_general_DF <= 4'b0;
		else if (!disable_DF && end_of_one_blk4x4_sum && blk4x4_rec_counter == 5'd22)
			mb_type_general_DF <= mb_type_general;
				
	reg [1:0] MB_inter_size;		
	always @ (mb_type_general_DF)	
		if (mb_type_general_DF[3] == 1'b0)
			case (mb_type_general_DF[2:0])
				3'b000,3'b101:MB_inter_size <= `I16x16;
				3'b001		 :MB_inter_size <= `I16x8;
				3'b010		 :MB_inter_size <= `I8x16;
				default		 :MB_inter_size <= `I8x8;
			endcase
		else //Although it should be Intra,but we have no other choice
			MB_inter_size <= `I8x8;
				
	reg [1:0] MBTypeGen_mbAddrB;		
	always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
		case (mb_num_h)
			0: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0];
			1: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
			2: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
			3: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
			4: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
			5: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
			6: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
			7: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
			8: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
			9: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
			10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
			default:MBTypeGen_mbAddrB <= 0;
		endcase	
		
	reg [1:0] bs_dec_counter;
	always @ (posedge gclk_bs_dec or negedge reset_n)
		if (reset_n == 1'b0)
			bs_dec_counter <= 0;
		else 
			bs_dec_counter <= bs_dec_counter - 1;
	
	assign end_of_BS_DEC = (bs_dec_counter == 2'd1)? 1'b1:1'b0;
	
	wire mvx_V0_diff_GE4,mvx_V1_diff_GE4,mvx_V2_diff_GE4,mvx_V3_diff_GE4;
	wire mvy_V0_diff_GE4,mvy_V1_diff_GE4,mvy_V2_diff_GE4,mvy_V3_diff_GE4;
	wire mvx_H0_diff_GE4,mvx_H1_diff_GE4,mvx_H2_diff_GE4,mvx_H3_diff_GE4;
	wire mvy_H0_diff_GE4,mvy_H1_diff_GE4,mvy_H2_diff_GE4,mvy_H3_diff_GE4;
	
	
	//--------------------------------------------------------------------
	//If current MB is Inter,derive current MB non-zero coeff information
	//No need to do this for P_skip or Intra.No need for chroma,either.
	//--------------------------------------------------------------------
	reg [15:0] currMB_coeff;//whether each 4x4blk of current MB has at least one non-zero transform coeff
							//currMB_coeff is organized in zig-zag order,according to blk4x4_rec_counter
							//= 1'b1:this 4x4blk has at least one non-zero transform coeff
							//= 1'b0:this 4x4blk has all 16 zero transform coeff
							//only useful for Inter (excluding P_skip) MB
	always @ (posedge clk)
		if (reset_n == 1'b0)
			currMB_coeff <= 16'd0;
		else if (!disable_DF)
			begin
				//need to be reset evey MB
				//Since only Inter MB needs currMB_coeff,we can use "coded_block_pattern_s" state as timing slot
				if (slice_data_state == `coded_block_pattern_s)
					currMB_coeff <= 16'd0;
				else if (mb_type_general[3] == 1'b0 && mb_type_general[2:0] != 3'b101)	//Inter but not P_skip
					case (residual_state)
						`Intra16x16ACLevel_s:
						if (end_of_one_residual_block)
							case (blk4x4_rec_counter[3:0])
								4'd0 :currMB_coeff[0]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd1 :currMB_coeff[1]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd2 :currMB_coeff[2]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd3 :currMB_coeff[3]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd4 :currMB_coeff[4]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd5 :currMB_coeff[5]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd6 :currMB_coeff[6]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd7 :currMB_coeff[7]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd8 :currMB_coeff[8]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd9 :currMB_coeff[9]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd10:currMB_coeff[10] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd11:currMB_coeff[11] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd12:currMB_coeff[12] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd13:currMB_coeff[13] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd14:currMB_coeff[14] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
								4'd15:currMB_coeff[15] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
							endcase		
						`Intra16x16ACLevel_0_s:
						case (blk4x4_rec_counter[3:0])
							4'd0:currMB_coeff[0]   <= ~curr_DC_IsZero;
							4'd1:currMB_coeff[1]   <= ~curr_DC_IsZero;
							4'd2:currMB_coeff[2]   <= ~curr_DC_IsZero;
							4'd3:currMB_coeff[3]   <= ~curr_DC_IsZero;
							4'd4:currMB_coeff[4]   <= ~curr_DC_IsZero;
							4'd5:currMB_coeff[5]   <= ~curr_DC_IsZero;
							4'd6:currMB_coeff[6]   <= ~curr_DC_IsZero;
							4'd7:currMB_coeff[7]   <= ~curr_DC_IsZero;
							4'd8:currMB_coeff[8]   <= ~curr_DC_IsZero;
							4'd9:currMB_coeff[9]   <= ~curr_DC_IsZero;
							4'd10:currMB_coeff[10] <= ~curr_DC_IsZero;
							4'd11:currMB_coeff[11] <= ~curr_DC_IsZero;
							4'd12:currMB_coeff[12] <= ~curr_DC_IsZero;
							4'd13:currMB_coeff[13] <= ~curr_DC_IsZero;
							4'd14:currMB_coeff[14] <= ~curr_DC_IsZero;
							4'd15:currMB_coeff[15] <= ~curr_DC_IsZero;
						endcase
						`LumaLevel_s:
						case (blk4x4_rec_counter[3:0])
							4'd0 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[0]  <= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[0]  <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd1 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[1] 	<= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[1]  <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd2 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[2] 	<= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[2]  <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd3 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[3] 	<= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[3]  <= (TotalCoeff == 0)? 1'b0:1'b1;
							4'd4 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[4] 	<= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[4]  <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd5 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[5] 	<= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[5]  <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd6 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[6] 	<= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[6]  <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd7 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[7] 	<= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[7]  <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd8 :if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[8] 	<= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[8]  <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd9 :if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[9] 	<= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[9]  <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd10:if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[10]	<= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[10] <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd11:if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[11] <= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[11] <= (TotalCoeff == 0)? 1'b0:1'b1;
							4'd12:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[12] <= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[12] <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd13:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[13] <= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[13] <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd14:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[14] <= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[14] <= (TotalCoeff == 0)? 1'b0:1'b1;	
							4'd15:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[15] <= 1'b0;
								  else if (end_of_one_residual_block)	currMB_coeff[15] <= (TotalCoeff == 0)? 1'b0:1'b1;		  
						endcase			  
					  	`LumaLevel_0_s:currMB_coeff <= 16'd0;
					endcase
			end
			
	//whether each 4x4blk of MB at mbAddrB has at least one non-zero transform coeff
	reg [43:0] mbAddrB_coeff_reg;
	always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
		if (reset_n == 1'b0)
			mbAddrB_coeff_reg <= 44'd0;
		else if (!disable_DF && mb_type_general[3] == 1'b0 && mb_type_general[2:0] != 3'b101 && mb_num_v != 8) //Inter but not P_skip
			case (mb_num_h)
				4'd0 :mbAddrB_coeff_reg[3:0]   <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
				4'd1 :mbAddrB_coeff_reg[7:4]   <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
				4'd2 :mbAddrB_coeff_reg[11:8]  <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
				4'd3 :mbAddrB_coeff_reg[15:12] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
				4'd4 :mbAddrB_coeff_reg[19:16] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
				4'd5 :mbAddrB_coeff_reg[23:20] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
				4'd6 :mbAddrB_coeff_reg[27:24] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
				4'd7 :mbAddrB_coeff_reg[31:28] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
				4'd8 :mbAddrB_coeff_reg[35:32] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
				4'd9 :mbAddrB_coeff_reg[39:36] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};