📄 nc_decoding.v
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case (i8x8) 1: case (i4x4) 1:LumaLevel_mbAddrA[4:0] <= TotalCoeff; 3:LumaLevel_mbAddrA[9:5] <= TotalCoeff; endcase 3: case (i4x4) 1:LumaLevel_mbAddrA[14:10] <= TotalCoeff; 3:LumaLevel_mbAddrA[19:15] <= TotalCoeff; endcase endcase //---------------------------- //ChromaLevel_Cb_mbAddrA write //---------------------------- always @ (posedge clk) if (reset_n == 0) ChromaLevel_Cb_mbAddrA <= 0; else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cb_s && mb_num_h != 10) begin if (i4x4_CbCr == 1) ChromaLevel_Cb_mbAddrA[4:0] <= TotalCoeff; if (i4x4_CbCr == 3) ChromaLevel_Cb_mbAddrA[9:5] <= TotalCoeff; end //---------------------------- //ChromaLevel_Cr_mbAddrA write //---------------------------- always @ (posedge clk) if (reset_n == 0) ChromaLevel_Cr_mbAddrA <= 0; else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cr_s && mb_num_h != 10) begin if (i4x4_CbCr == 1) ChromaLevel_Cr_mbAddrA[4:0] <= TotalCoeff; if (i4x4_CbCr == 3) ChromaLevel_Cr_mbAddrA[9:5] <= TotalCoeff; end //------------------------------ //LumaLevel_mbAddrB read & write //------------------------------ always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or Luma_8x8_AllZeroCoeff_mbAddrB or i8x8 or i4x4 or end_of_one_residual_block or mb_num_v or mb_num_h or CodedBlockPatternLuma or LumaLevel_CurrMb2 or LumaLevel_CurrMb3 or TotalCoeff) if (reset_n == 0) begin LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end //--read-- else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1) //read case (residual_state) `Intra16x16DCLevel_s: if (Luma_8x8_AllZeroCoeff_mbAddrB == 0) begin LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end else begin LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end `Intra16x16ACLevel_s,`LumaLevel_s: case (i8x8) 0: if (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0) begin LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end else begin LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end 1: if (Luma_8x8_AllZeroCoeff_mbAddrB[1] == 0) begin LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end else begin LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end default: begin LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end endcase default: begin LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end endcase //--write-- else if ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && end_of_one_residual_block == 1 && mb_num_v != 8) case (CodedBlockPatternLuma[3:2]) 2'b00: begin LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end 2'b10,2'b11: if (i8x8 == 3 && i4x4 == 3) begin LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 0; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= mb_num_h; LumaLevel_mbAddrB_din <= (CodedBlockPatternLuma[3:2] == 2'b10)? {10'b0, LumaLevel_CurrMb3[14:10],TotalCoeff}: {LumaLevel_CurrMb2[14:10],LumaLevel_CurrMb2[19:15],LumaLevel_CurrMb3[14:10],TotalCoeff}; end else begin LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end 2'b01: if (i8x8 == 2 && i4x4 == 3) begin LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 0; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= mb_num_h; LumaLevel_mbAddrB_din <= {LumaLevel_CurrMb2[14:10],TotalCoeff,10'b0}; end else begin LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end endcase else begin LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; LumaLevel_mbAddrB_din <= 0; end //----------------------------------- //ChromaLevel_Cb_mbAddrB read & write //----------------------------------- always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or i4x4_CbCr or ChromaLevel_Cb_CurrMb or Chroma_8x8_AllZeroCoeff_mbAddrB or mb_num_h or mb_num_v or TotalCoeff or end_of_one_residual_block) if (reset_n == 0) begin ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; ChromaLevel_Cb_mbAddrB_din <= 0; end //--read-- else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1 && residual_state == `ChromaACLevel_Cb_s) begin if (i4x4_CbCr[1] == 0 && Chroma_8x8_AllZeroCoeff_mbAddrB == 1) begin ChromaLevel_Cb_mbAddrB_cs_n <= 0; ChromaLevel_Cb_mbAddrB_wr_n <= 1; ChromaLevel_Cb_mbAddrB_rd_addr <= mb_num_h; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; ChromaLevel_Cb_mbAddrB_din <= 0; end else begin ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; ChromaLevel_Cb_mbAddrB_din <= 0; end end //--write-- else if (residual_state == `ChromaACLevel_Cb_s && end_of_one_residual_block == 1 && mb_num_v != 8) begin if (i4x4_CbCr == 3) begin ChromaLevel_Cb_mbAddrB_cs_n <= 0; ChromaLevel_Cb_mbAddrB_wr_n <= 0; ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= mb_num_h; ChromaLevel_Cb_mbAddrB_din <= {ChromaLevel_Cb_CurrMb[14:10],TotalCoeff}; end else begin ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; ChromaLevel_Cb_mbAddrB_din <= 0; end end else begin ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; ChromaLevel_Cb_mbAddrB_din <= 0; end //----------------------------------- //ChromaLevel_Cr_mbAddrB read & write //----------------------------------- always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or i4x4_CbCr or ChromaLevel_Cr_CurrMb or Chroma_8x8_AllZeroCoeff_mbAddrB or mb_num_h or mb_num_v or TotalCoeff or end_of_one_residual_block) if (reset_n == 0) begin ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; ChromaLevel_Cr_mbAddrB_din <= 0; end //--read-- else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1 && residual_state == `ChromaACLevel_Cr_s) //read begin if (i4x4_CbCr[1] == 0 && Chroma_8x8_AllZeroCoeff_mbAddrB == 1) begin ChromaLevel_Cr_mbAddrB_cs_n <= 0; ChromaLevel_Cr_mbAddrB_wr_n <= 1; ChromaLevel_Cr_mbAddrB_rd_addr <= mb_num_h; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; ChromaLevel_Cr_mbAddrB_din <= 0; end else begin ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; ChromaLevel_Cr_mbAddrB_din <= 0; end end //--write-- else if (residual_state == `ChromaACLevel_Cr_s && end_of_one_residual_block == 1 && mb_num_v != 8) begin if (i4x4_CbCr == 3) begin ChromaLevel_Cr_mbAddrB_cs_n <= 0; ChromaLevel_Cr_mbAddrB_wr_n <= 0; ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= mb_num_h; ChromaLevel_Cr_mbAddrB_din <= {ChromaLevel_Cr_CurrMb[14:10],TotalCoeff}; end else begin ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; ChromaLevel_Cr_mbAddrB_din <= 0; end end else begin ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; ChromaLevel_Cr_mbAddrB_din <= 0; endendmodule
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