nc_decoding.v

a H.264/AVC Baseline Decoder

//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : [e-mail]
// File      : nC_decoding.v
// Generated : May 18, 2005
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Devive the number of none-zero coeff during nC decoding for TotalCoeff & TrailingOnes LUT
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module nC_decoding (clk,reset_n,gclk_end_of_MB_DEC,
	cavlc_decoder_state,residual_state,slice_data_state,
	mb_num_h,mb_num_v,i8x8,i4x4,i4x4_CbCr,CodedBlockPatternLuma,CodedBlockPatternChroma,
	LumaLevel_mbAddrB_dout,ChromaLevel_Cb_mbAddrB_dout,ChromaLevel_Cr_mbAddrB_dout,
	end_of_one_residual_block,TotalCoeff,
	
	nC,
	Luma_8x8_AllZeroCoeff_mbAddrA,LumaLevel_mbAddrA,
	LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3,
	LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n,LumaLevel_mbAddrB_rd_addr,
	LumaLevel_mbAddrB_wr_addr,LumaLevel_mbAddrB_din,
	ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n,ChromaLevel_Cb_mbAddrB_rd_addr,
	ChromaLevel_Cb_mbAddrB_wr_addr,ChromaLevel_Cb_mbAddrB_din,
	ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n,ChromaLevel_Cr_mbAddrB_rd_addr,
	ChromaLevel_Cr_mbAddrB_wr_addr,ChromaLevel_Cr_mbAddrB_din);
	
	input clk,reset_n;
	input gclk_end_of_MB_DEC;
	input [3:0] cavlc_decoder_state;
	input [3:0] residual_state;
	input [3:0] slice_data_state;
	input [3:0] mb_num_h;
	input [3:0] mb_num_v;
	input [1:0] i8x8,i4x4;
	input [1:0] i4x4_CbCr;
	input [3:0] CodedBlockPatternLuma;
	input [1:0] CodedBlockPatternChroma;
	input [19:0] LumaLevel_mbAddrB_dout;
	input [9:0]  ChromaLevel_Cb_mbAddrB_dout,ChromaLevel_Cr_mbAddrB_dout;
	input end_of_one_residual_block;
	input [4:0] TotalCoeff;
	
	output [4:0] nC;
	output [1:0] Luma_8x8_AllZeroCoeff_mbAddrA;
	output [19:0] LumaLevel_mbAddrA;
	output [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3;
	output LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n;
	output [3:0] LumaLevel_mbAddrB_rd_addr,LumaLevel_mbAddrB_wr_addr;
	output [19:0]LumaLevel_mbAddrB_din;
	output ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n;
	output [3:0] ChromaLevel_Cb_mbAddrB_rd_addr,ChromaLevel_Cb_mbAddrB_wr_addr;
	output [9:0] ChromaLevel_Cb_mbAddrB_din;
	output ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n;
	output [3:0] ChromaLevel_Cr_mbAddrB_rd_addr,ChromaLevel_Cr_mbAddrB_wr_addr;
	output [9:0] ChromaLevel_Cr_mbAddrB_din;
	
	reg [4:0] nC;
	reg LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n;
	reg [3:0] LumaLevel_mbAddrB_rd_addr,LumaLevel_mbAddrB_wr_addr;
	reg [19:0]LumaLevel_mbAddrB_din;
	reg ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n;
	reg [3:0] ChromaLevel_Cb_mbAddrB_rd_addr,ChromaLevel_Cb_mbAddrB_wr_addr;
	reg [9:0] ChromaLevel_Cb_mbAddrB_din;
	reg ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n;
	reg [3:0] ChromaLevel_Cr_mbAddrB_rd_addr,ChromaLevel_Cr_mbAddrB_wr_addr;
	reg [9:0] ChromaLevel_Cr_mbAddrB_din;
		
	reg nA_availability,nB_availability;
	reg nA_availability_reg,nB_availability_reg;
	reg [4:0]  nA,nB;
	reg [19:0] LumaLevel_mbAddrA;
	reg [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3;
	reg [19:0] ChromaLevel_Cb_CurrMb;
	reg [9:0]  ChromaLevel_Cb_mbAddrA;
	reg [19:0] ChromaLevel_Cr_CurrMb;
	reg [9:0]  ChromaLevel_Cr_mbAddrA;
	reg [1:0]  Luma_8x8_AllZeroCoeff_mbAddrA;
	reg [0:21] Luma_8x8_AllZeroCoeff_mbAddrB_reg;
	reg [0:1]  Luma_8x8_AllZeroCoeff_mbAddrB;
	reg	Chroma_8x8_AllZeroCoeff_mbAddrA;
	reg [10:0] Chroma_8x8_AllZeroCoeff_mbAddrB_reg;
	reg Chroma_8x8_AllZeroCoeff_mbAddrB;
	
	always @ (mb_num_h or Luma_8x8_AllZeroCoeff_mbAddrB_reg)
		case (mb_num_h)
			0 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[0:1];
			1 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[2:3];
			2 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[4:5];
			3 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[6:7];
			4 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[8:9];
			5 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[10:11];
			6 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[12:13];
			7 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[14:15];
			8 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[16:17];
			9 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[18:19];
			10:Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[20:21];
			default:Luma_8x8_AllZeroCoeff_mbAddrB <= 0;
		endcase
	always @ (mb_num_h or Chroma_8x8_AllZeroCoeff_mbAddrB_reg)
		case (mb_num_h)
			0 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0];
			1 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1];
			2 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2];
			3 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3];
			4 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4];
			5 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5];
			6 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6];
			7 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7];
			8 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8];
			9 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9];
			10:Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10];
			default:Chroma_8x8_AllZeroCoeff_mbAddrB <= 0;
		endcase
	//----------------------------
	//Update 8x8_AllZero registers
	//----------------------------
	always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
		if (reset_n == 0)	
			Luma_8x8_AllZeroCoeff_mbAddrA <= 0;
		else if (slice_data_state == `skip_run_duration)
			Luma_8x8_AllZeroCoeff_mbAddrA <= 0;
		else //update 8x8_AllZero reg when finished one MB residual parsing
			begin
				Luma_8x8_AllZeroCoeff_mbAddrA[0] <= (CodedBlockPatternLuma[1] == 0)? 1'b0:1'b1;
				Luma_8x8_AllZeroCoeff_mbAddrA[1] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
			end
	always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
		if (reset_n == 0)
			Luma_8x8_AllZeroCoeff_mbAddrB_reg <= 0;
		else if (slice_data_state == `skip_run_duration)
			case (mb_num_h)
				0 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[0:1]   <= 0;
				1 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[2:3]   <= 0;
				2 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[4:5]   <= 0;
				3 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[6:7]   <= 0;
				4 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[8:9]   <= 0;
				5 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[10:11] <= 0;
				6 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[12:13] <= 0;
				7 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[14:15] <= 0;
				8 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[16:17] <= 0;
				9 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[18:19] <= 0;
				10:Luma_8x8_AllZeroCoeff_mbAddrB_reg[20:21] <= 0;
			endcase
		else  //update 8x8_AllZero reg when finished one MB residual parsing
			case (mb_num_h)
				0:
				begin
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [0] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [1] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
				end
				1:
				begin
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [2] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [3] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
				end
				2:
				begin
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [4] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [5] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
				end
				3:
				begin
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [6] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [7] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
				end
				4:
				begin
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [8] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [9] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
				end
				5:
				begin
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [10] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [11] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
				end
				6:
				begin
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [12] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [13] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
				end
				7:
				begin
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [14] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [15] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
				end
				8:
				begin
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [16] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [17] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
				end
				9:
				begin
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [18] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [19] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
				end
				10:
				begin
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [20] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1;
					Luma_8x8_AllZeroCoeff_mbAddrB_reg [21] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1;
				end
			endcase
	always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
		if (reset_n == 0)	
			Chroma_8x8_AllZeroCoeff_mbAddrA <= 0;
		else if (slice_data_state == `skip_run_duration)
			Chroma_8x8_AllZeroCoeff_mbAddrA <= 0;
		else  //update 8x8_AllZero reg when finished one MB residual parsing
			Chroma_8x8_AllZeroCoeff_mbAddrA <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
	always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
		if (reset_n == 0)
			Chroma_8x8_AllZeroCoeff_mbAddrB_reg <= 0;
		else if (slice_data_state == `skip_run_duration)
			case (mb_num_h)
				0 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0]  <= 0;
				1 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1]  <= 0;
				2 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2]  <= 0;
				3 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3]  <= 0;
				4 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4]  <= 0;
				5 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5]  <= 0;
				6 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6]  <= 0;
				7 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7]  <= 0;
				8 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8]  <= 0;
				9 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9]  <= 0;
				10:Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10] <= 0;
			endcase
		else if (mb_num_v != 8)
			case (mb_num_h)
				0 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0]  <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
				1 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1]  <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
				2 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2]  <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
				3 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3]  <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
				4 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4]  <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
				5 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5]  <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
				6 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6]  <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
				7 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7]  <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
				8 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8]  <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
				9 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9]  <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
				10:Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1;
			endcase
	//-------------------
	//nA_availability
	//-------------------
	always @ (posedge clk)
		if (reset_n == 0)
			nA_availability_reg <= 0;
		else if (cavlc_decoder_state == `nAnB_decoding_s)
			nA_availability_reg <= nA_availability;