intra_pred_reg_ctrl.v

a H.264/AVC Baseline Decoder

							Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
							Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
						end
					endcase
				//Chroma Cb/Cr Horizontal & DC
				else if (blk4x4_rec_counter > 15 && blk4x4_intra_calculate_counter != 0 &&
					(Intra_chroma_predmode == `Intra_chroma_Horizontal || (Intra_chroma_predmode == `Intra_chroma_DC && mbAddrA_availability)))
					case (blk4x4_rec_counter)
						16,17:
						begin
							Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg0;
							Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg1;
							Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg2;
							Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg3;
						end
						18,19:
						begin
							Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg4;
							Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg5;
							Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg6;
							Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg7;
						end
						20,21:
						begin
							Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg0;
							Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg1;
							Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg2;
							Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg3;
						end
						22,23:
						begin
							Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg4;
							Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg5;
							Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg6;
							Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg7;
						end
						default:
						begin
							Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
							Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
						end
					endcase
				else
					begin
						Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
						Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
					end
			end
		else
			begin
				Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
				Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
			end
			
	
	//Intra_mbAddrB_window0 ~ 3
	always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode
		or blk4x4_intra_calculate_counter or blk4x4_rec_counter	
		or Intra_mbAddrB_reg0  or Intra_mbAddrB_reg1  or Intra_mbAddrB_reg2 
		or Intra_mbAddrB_reg3  or Intra_mbAddrB_reg4  or Intra_mbAddrB_reg5
		or Intra_mbAddrB_reg6  or Intra_mbAddrB_reg7  or Intra_mbAddrB_reg8
		or Intra_mbAddrB_reg9  or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
		or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14
		or Intra_mbAddrB_reg15)
		if (mb_type_general[3] == 1'b1)
			begin
				//Intra4x4 && Intra16x16_Vertical
				if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 && 
					(mb_type_general[2] == 1'b1 || (
					(mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Vertical))))
					case (blk4x4_rec_counter)
						0,2,8,10:
						begin
							Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0;
							Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1;
							Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2;
							Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3;
						end
						1,3,9,11:
						begin
							Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4;
							Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5;
							Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6;
							Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7;
						end
						4,6,12,14:
						begin
							Intra_mbAddrB_window0 <= Intra_mbAddrB_reg8;
							Intra_mbAddrB_window1 <= Intra_mbAddrB_reg9;
							Intra_mbAddrB_window2 <= Intra_mbAddrB_reg10;
							Intra_mbAddrB_window3 <= Intra_mbAddrB_reg11;
						end
						5,7,13,15:
						begin
							Intra_mbAddrB_window0 <= Intra_mbAddrB_reg12;
							Intra_mbAddrB_window1 <= Intra_mbAddrB_reg13;
							Intra_mbAddrB_window2 <= Intra_mbAddrB_reg14;
							Intra_mbAddrB_window3 <= Intra_mbAddrB_reg15;
						end
						default:
						begin
							Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
							Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
						end
					endcase
				//Chroma Cb/Cr Vertical and DC
				else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 24 && 
					(Intra_chroma_predmode == `Intra_chroma_Vertical || Intra_chroma_predmode == `Intra_chroma_DC) && blk4x4_intra_calculate_counter != 0)
					case (blk4x4_rec_counter)
						16,18,20,22:
						begin
							Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0;
							Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1;
							Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2;
							Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3;
						end
						17,19,21,23:
						begin
							Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4;
							Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5;
							Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6;
							Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7;
						end
						default:
						begin
							Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
							Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
						end
					endcase
				else
					begin
						Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
						Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
					end
			end
		else
			begin
				Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
				Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
			end
	//Intra_mbAddrC_window0 ~ 3
	always @ (mb_type_general[3:2] or blk4x4_intra_calculate_counter or blk4x4_rec_counter or Intra4x4_predmode 
		or Intra_mbAddrC_reg0  or Intra_mbAddrC_reg1  or Intra_mbAddrC_reg2  or Intra_mbAddrC_reg3
		or Intra_mbAddrB_reg4  or Intra_mbAddrB_reg5  or Intra_mbAddrB_reg6  or Intra_mbAddrB_reg7  
		or Intra_mbAddrB_reg8  or Intra_mbAddrB_reg9  or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
		or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15
		or mbAddrC_availability or Intra_mbAddrB_window3)
		if (mb_type_general[3:2] == 2'b11 && blk4x4_intra_calculate_counter != 0 && (
			Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left || Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter < 16)
			case (blk4x4_rec_counter)
				0,1,4:
				begin
					Intra_mbAddrC_window0 <= Intra_mbAddrC_reg0;
					Intra_mbAddrC_window1 <= Intra_mbAddrC_reg1;
					Intra_mbAddrC_window2 <= Intra_mbAddrC_reg2;
					Intra_mbAddrC_window3 <= Intra_mbAddrC_reg3;
				end
				5:
				begin
					Intra_mbAddrC_window0 <= (mbAddrC_availability)? Intra_mbAddrC_reg0:Intra_mbAddrB_reg15;
					Intra_mbAddrC_window1 <= (mbAddrC_availability)? Intra_mbAddrC_reg1:Intra_mbAddrB_reg15;
					Intra_mbAddrC_window2 <= (mbAddrC_availability)? Intra_mbAddrC_reg2:Intra_mbAddrB_reg15;
					Intra_mbAddrC_window3 <= (mbAddrC_availability)? Intra_mbAddrC_reg3:Intra_mbAddrB_reg15;
				end
				2,8,10:
				begin
					Intra_mbAddrC_window0  <= Intra_mbAddrB_reg4;
					Intra_mbAddrC_window1  <= Intra_mbAddrB_reg5;
					Intra_mbAddrC_window2  <= Intra_mbAddrB_reg6;
					Intra_mbAddrC_window3  <= Intra_mbAddrB_reg7;
				end
				9: 
				begin
					Intra_mbAddrC_window0  <= Intra_mbAddrB_reg8;
					Intra_mbAddrC_window1  <= Intra_mbAddrB_reg9;
					Intra_mbAddrC_window2  <= Intra_mbAddrB_reg10;
					Intra_mbAddrC_window3  <= Intra_mbAddrB_reg11;
				end
				6,12,14:
				begin
					Intra_mbAddrC_window0  <= Intra_mbAddrB_reg12;
					Intra_mbAddrC_window1  <= Intra_mbAddrB_reg13;
					Intra_mbAddrC_window2  <= Intra_mbAddrB_reg14;
					Intra_mbAddrC_window3  <= Intra_mbAddrB_reg15;
				end
				3,11,7,13,15:
				begin
					Intra_mbAddrC_window0  <= Intra_mbAddrB_window3;
					Intra_mbAddrC_window1  <= Intra_mbAddrB_window3;
					Intra_mbAddrC_window2  <= Intra_mbAddrB_window3;
					Intra_mbAddrC_window3  <= Intra_mbAddrB_window3;
				end
				default:
				begin
					Intra_mbAddrC_window0  <= 0;	Intra_mbAddrC_window1  <= 0;
					Intra_mbAddrC_window2  <= 0;	Intra_mbAddrC_window3  <= 0;
				end
			endcase
		else
			begin
				Intra_mbAddrC_window0  <= 0;	Intra_mbAddrC_window1  <= 0;
				Intra_mbAddrC_window2  <= 0;	Intra_mbAddrC_window3  <= 0;
			end
	
	//Intra_mbAddrD_window
	always @ (mb_type_general[3:2] or blk4x4_rec_counter 
		or blk4x4_intra_calculate_counter or blk4x4_intra_precompute_counter 
		or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode
		or Intra_mbAddrD_reg0 or Intra_mbAddrD_reg1 or Intra_mbAddrD_reg2 
		or Intra_mbAddrD_reg3 or Intra_mbAddrD_reg4 
		or Intra_mbAddrD_LeftMB_luma_reg or Intra_mbAddrD_LeftMB_Cb_reg or Intra_mbAddrD_LeftMB_Cr_reg)
		//Intra
		if (mb_type_general[3] == 1'b1 && (blk4x4_intra_calculate_counter != 0 || blk4x4_intra_precompute_counter != 0))
			begin
				//Intra luma
				if (blk4x4_rec_counter[4] == 1'b0)
					begin
						//Intra4x4 luma
						if (mb_type_general[2] == 1'b1 && (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Right || 
                                               Intra4x4_predmode == `Intra4x4_Vertical_Right      || 
                                               Intra4x4_predmode == `Intra4x4_Horizontal_Down))
							case (blk4x4_rec_counter[3:0])
								0,2,8,10:Intra_mbAddrD_window <= Intra_mbAddrD_LeftMB_luma_reg;
								3,5,13	:Intra_mbAddrD_window <= Intra_mbAddrD_reg0;
								1,6,11	:Intra_mbAddrD_window <= Intra_mbAddrD_reg1;
								9,15	:Intra_mbAddrD_window <= Intra_mbAddrD_reg2;
								12 		:Intra_mbAddrD_window <= Intra_mbAddrD_reg3;
								4,7,14	:Intra_mbAddrD_window <= Intra_mbAddrD_reg4;
							endcase
						//Intra16x16
						else 
							Intra_mbAddrD_window <= (Intra16x16_predmode == `Intra16x16_Plane)? Intra_mbAddrD_LeftMB_luma_reg:0;
					end
				//Intra chroma
				else if (blk4x4_rec_counter > 15 && Intra_chroma_predmode == `Intra_chroma_Plane)
					Intra_mbAddrD_window <= (blk4x4_rec_counter < 20)? Intra_mbAddrD_LeftMB_Cb_reg:Intra_mbAddrD_LeftMB_Cr_reg;
				else
					Intra_mbAddrD_window <= 0;
			end
		//Inter
		else
			Intra_mbAddrD_window <= 0;
	
	//seed
	always @ (posedge gclk_seed or negedge reset_n)
		if (reset_n == 1'b0)
			begin
				seed_0 <= 0;	seed_1 <= 0;	seed_2 <= 0;
			end
		else if (blk4x4_intra_precompute_counter == 1)
			seed_0 <= main_seed;
		else
			case (blk4x4_rec_counter)
				0,2,8,16,20	:seed_0 <= PE3_sum_out;
				1,9			:seed_1 <= PE0_sum_out; 
				3,11		:seed_2 <= PE0_sum_out;
			endcase
			
	always @ (mb_type_general[3:2] or Intra16x16_predmode or Intra_chroma_predmode
		or blk4x4_intra_calculate_counter or blk4x4_rec_counter or seed_0 or seed_1 or seed_2)
		if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter < 16)
			case (blk4x4_rec_counter)
				0,2,8,10:seed <= seed_0;
				4,12	:seed <= seed_1;
				6,14	:seed <= seed_2;
				default :seed <= 0;
			endcase
		else if (mb_type_general[3] == 1'b1 && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter > 15)
			if (blk4x4_rec_counter[0] == 1'b0)	//16,18,20,22
				seed <= seed_0;
			else
				seed <= 0;
		else
			seed <= 0;
		
endmodule