intra_pred_reg_ctrl.v

a H.264/AVC Baseline Decoder

							Intra_mbAddrB_reg15 <= blk4x4_sum_PE3_out;
						end
					endcase
			end
		//Intra16x16
		else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
			case (blk4x4_intra_preload_counter)
				3'b100:	
				begin
					Intra_mbAddrB_reg0  <= Intra_mbAddrB_RAM_dout[7:0];
					Intra_mbAddrB_reg1  <= Intra_mbAddrB_RAM_dout[15:8];
					Intra_mbAddrB_reg2  <= Intra_mbAddrB_RAM_dout[23:16];
					Intra_mbAddrB_reg3  <= Intra_mbAddrB_RAM_dout[31:24];
				end
				3'b011:
				begin
					Intra_mbAddrB_reg4  <= Intra_mbAddrB_RAM_dout[7:0];
					Intra_mbAddrB_reg5  <= Intra_mbAddrB_RAM_dout[15:8];
					Intra_mbAddrB_reg6  <= Intra_mbAddrB_RAM_dout[23:16];
					Intra_mbAddrB_reg7  <= Intra_mbAddrB_RAM_dout[31:24];
				end
				3'b010:
				begin
					Intra_mbAddrB_reg8  <= Intra_mbAddrB_RAM_dout[7:0];
					Intra_mbAddrB_reg9  <= Intra_mbAddrB_RAM_dout[15:8];
					Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16];
					Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24];
				end
				3'b001:
				begin
					Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0];
					Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8];
					Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16];
					Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24];
				end
			endcase	
		//Chroma
		else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15)
			begin
				if (blk4x4_intra_preload_counter == 3'b010)
					begin
						Intra_mbAddrB_reg0  <= Intra_mbAddrB_RAM_dout[7:0];
						Intra_mbAddrB_reg1  <= Intra_mbAddrB_RAM_dout[15:8];
						Intra_mbAddrB_reg2  <= Intra_mbAddrB_RAM_dout[23:16];
						Intra_mbAddrB_reg3  <= Intra_mbAddrB_RAM_dout[31:24];
					end
				else if (blk4x4_intra_preload_counter == 3'b001)
					begin
						Intra_mbAddrB_reg4  <= Intra_mbAddrB_RAM_dout[7:0];
						Intra_mbAddrB_reg5  <= Intra_mbAddrB_RAM_dout[15:8];
						Intra_mbAddrB_reg6  <= Intra_mbAddrB_RAM_dout[23:16];
						Intra_mbAddrB_reg7  <= Intra_mbAddrB_RAM_dout[31:24];
					end	
			end	
	//--------------------------------------------------------
	//Intra_mbAddrC_reg0 ~ 3,only useful for Intra4x4 with
	// blkIdx = 0/1/4/5
	//--------------------------------------------------------

	always @ (posedge gclk_intra_mbAddrC_luma or negedge reset_n)
		if (reset_n == 1'b0)
			begin
				Intra_mbAddrC_reg0  <= 0;	Intra_mbAddrC_reg1  <= 0; 
				Intra_mbAddrC_reg2  <= 0;	Intra_mbAddrC_reg3  <= 0;
			end
		else 
			begin
				Intra_mbAddrC_reg0  <= Intra_mbAddrB_RAM_dout[7:0];
				Intra_mbAddrC_reg1  <= Intra_mbAddrB_RAM_dout[15:8];
				Intra_mbAddrC_reg2  <= Intra_mbAddrB_RAM_dout[23:16];
				Intra_mbAddrC_reg3  <= Intra_mbAddrB_RAM_dout[31:24];
			end
	//--------------------------------------------------------
	//Intra_mbAddrD_reg0 ~ 5
	//Intra_mbAddrD_LeftMB_reg
	//--------------------------------------------------------
	always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
		if (reset_n == 1'b0)
			Intra_mbAddrD_LeftMB_luma_reg <= 0;
		else if (blk4x4_rec_counter == 15)
			Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrB_RAM_dout[31:24];
		else if (mb_type_general[3:2] == 2'b11 && blk4x4_sum_counter == 3'd3)	//Intra4x4
			case (blk4x4_rec_counter)
				0:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg3;
				2:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg7;
				8:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg11;
			endcase

	always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
		if (reset_n == 1'b0)
			Intra_mbAddrD_LeftMB_Cb_reg <= 0;
		else if (blk4x4_rec_counter == 19)
			Intra_mbAddrD_LeftMB_Cb_reg <= Intra_mbAddrB_RAM_dout[31:24];
			
	always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
		if (reset_n == 1'b0)
			Intra_mbAddrD_LeftMB_Cr_reg <= 0;
		else if (blk4x4_rec_counter == 23)
			Intra_mbAddrD_LeftMB_Cr_reg <= Intra_mbAddrB_RAM_dout[31:24];		
			
	always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
		if (reset_n == 1'b0)
			begin 
				Intra_mbAddrD_reg0 <= 0; Intra_mbAddrD_reg1 <= 0; Intra_mbAddrD_reg2 <= 0;	
				Intra_mbAddrD_reg3 <= 0; Intra_mbAddrD_reg4 <= 0; 
			end
		else if (mb_type_general[3:2] == 2'b11)
			begin
				//load from Intra_mbAddrB_RAM for blk 1/4/5
				if (blk4x4_intra_preload_counter == 3'b010)
					case (blk4x4_rec_counter)
						1:Intra_mbAddrD_reg1 <= Intra_mbAddrB_RAM_dout[31:24];
						4:Intra_mbAddrD_reg4 <= Intra_mbAddrB_RAM_dout[31:24];
						5:Intra_mbAddrD_reg0 <= Intra_mbAddrB_RAM_dout[31:24];
					endcase
				//update Intra_mbAddrD_reg by pixels already decoded from left up blk4x4
				//After sum of blk0/1/4, update Intra_mbAddrD_reg0/1/2 for blkIdx 3 /6 /7
				//After sum of blk2/3/6, update Intra_mbAddrD_reg3/4/5 for blkIdx 9 /12/13
				//After sum of blk8/9/12,update Intra_mbAddrD_reg0/1/2 for blkIdx 11/14/15
				else
					case (blk4x4_rec_counter)
						0,6 :Intra_mbAddrD_reg0 <= blk4x4_sum_PE3_out;
						1,8 :Intra_mbAddrD_reg1 <= blk4x4_sum_PE3_out;
						2,12:Intra_mbAddrD_reg2 <= blk4x4_sum_PE3_out;
						3   :Intra_mbAddrD_reg3 <= blk4x4_sum_PE3_out;
						4,9	:Intra_mbAddrD_reg4 <= blk4x4_sum_PE3_out;
					endcase
			end
	//---------------------------
	//sliding window output
	//---------------------------
	//Intra_mbAddrA_reg0 ~ 15
	always @ (mb_type_general[3:2] or blk4x4_rec_counter or blk4x4_intra_calculate_counter or 
		blk4x4_intra_precompute_counter or Intra16x16_predmode or Intra_chroma_predmode
		or mbAddrA_availability
		
		or Intra_mbAddrA_luma_reg0  or Intra_mbAddrA_luma_reg1  or Intra_mbAddrA_luma_reg2 
		or Intra_mbAddrA_luma_reg3  or Intra_mbAddrA_luma_reg4  or Intra_mbAddrA_luma_reg5
		or Intra_mbAddrA_luma_reg6  or Intra_mbAddrA_luma_reg7  or Intra_mbAddrA_luma_reg8
		or Intra_mbAddrA_luma_reg9  or Intra_mbAddrA_luma_reg10 or Intra_mbAddrA_luma_reg11
		or Intra_mbAddrA_luma_reg12 or Intra_mbAddrA_luma_reg13 or Intra_mbAddrA_luma_reg14
		or Intra_mbAddrA_luma_reg15
		
		or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2
		or Intra_mbAddrA_Cb_reg3 or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5
		or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7
		
		or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2
		or Intra_mbAddrA_Cr_reg3 or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5
		or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7)
		if (mb_type_general[3] == 1'b1)
			begin
				//Intra4x4
				//Intra16x16_Horizontal,Intra16x16_DC,Intra16x16_Plane
				if (blk4x4_rec_counter < 16 && 
					(mb_type_general[2] == 1'b1 || (mb_type_general[2] == 1'b0 && (
					(Intra16x16_predmode == `Intra16x16_Horizontal && blk4x4_intra_calculate_counter  != 0) ||
					(Intra16x16_predmode == `Intra16x16_DC 	 	     && blk4x4_intra_calculate_counter  != 0 && mbAddrA_availability == 1'b1) ||
					(Intra16x16_predmode == `Intra16x16_Plane      && blk4x4_intra_precompute_counter != 0)))))
					begin
						Intra_mbAddrA_reg0  <= Intra_mbAddrA_luma_reg0;
						Intra_mbAddrA_reg1  <= Intra_mbAddrA_luma_reg1;
						Intra_mbAddrA_reg2  <= Intra_mbAddrA_luma_reg2;
						Intra_mbAddrA_reg3  <= Intra_mbAddrA_luma_reg3;
						Intra_mbAddrA_reg4  <= Intra_mbAddrA_luma_reg4;
						Intra_mbAddrA_reg5  <= Intra_mbAddrA_luma_reg5;
						Intra_mbAddrA_reg6  <= Intra_mbAddrA_luma_reg6;
						Intra_mbAddrA_reg7  <= Intra_mbAddrA_luma_reg7;
						Intra_mbAddrA_reg8  <= Intra_mbAddrA_luma_reg8;
						Intra_mbAddrA_reg9  <= Intra_mbAddrA_luma_reg9;
						Intra_mbAddrA_reg10 <= Intra_mbAddrA_luma_reg10;
						Intra_mbAddrA_reg11 <= Intra_mbAddrA_luma_reg11;
						Intra_mbAddrA_reg12 <= Intra_mbAddrA_luma_reg12;
						Intra_mbAddrA_reg13 <= Intra_mbAddrA_luma_reg13;
						Intra_mbAddrA_reg14 <= Intra_mbAddrA_luma_reg14;
						Intra_mbAddrA_reg15 <= Intra_mbAddrA_luma_reg15;
					end
				//Chroma Cb
				else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 20 && (
					(Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter  != 0) ||
					(Intra_chroma_predmode == `Intra_chroma_DC         && blk4x4_intra_calculate_counter  != 0 && mbAddrA_availability == 1'b1) 														   ||
					(Intra_chroma_predmode == `Intra_chroma_Plane      && blk4x4_intra_precompute_counter != 0)))
					begin
						Intra_mbAddrA_reg0  <= Intra_mbAddrA_Cb_reg0;
						Intra_mbAddrA_reg1  <= Intra_mbAddrA_Cb_reg1;
						Intra_mbAddrA_reg2  <= Intra_mbAddrA_Cb_reg2;
						Intra_mbAddrA_reg3  <= Intra_mbAddrA_Cb_reg3;
						Intra_mbAddrA_reg4  <= Intra_mbAddrA_Cb_reg4;
						Intra_mbAddrA_reg5  <= Intra_mbAddrA_Cb_reg5;
						Intra_mbAddrA_reg6  <= Intra_mbAddrA_Cb_reg6;
						Intra_mbAddrA_reg7  <= Intra_mbAddrA_Cb_reg7;
						Intra_mbAddrA_reg8  <= 0;	Intra_mbAddrA_reg9  <= 0;
						Intra_mbAddrA_reg10 <= 0;	Intra_mbAddrA_reg11 <= 0;
						Intra_mbAddrA_reg12 <= 0;	Intra_mbAddrA_reg13 <= 0;
						Intra_mbAddrA_reg14 <= 0;	Intra_mbAddrA_reg15 <= 0;
					end
				//Chroma Cr
				else if (blk4x4_rec_counter > 19 && blk4x4_rec_counter < 24 && (
					(Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter  != 0) ||
					(Intra_chroma_predmode == `Intra_chroma_DC         && blk4x4_intra_calculate_counter  != 0 && mbAddrA_availability == 1'b1) 														   ||
					(Intra_chroma_predmode == `Intra_chroma_Plane      && blk4x4_intra_precompute_counter != 0)))
					begin
						Intra_mbAddrA_reg0  <= Intra_mbAddrA_Cr_reg0;
						Intra_mbAddrA_reg1  <= Intra_mbAddrA_Cr_reg1;
						Intra_mbAddrA_reg2  <= Intra_mbAddrA_Cr_reg2;
						Intra_mbAddrA_reg3  <= Intra_mbAddrA_Cr_reg3;
						Intra_mbAddrA_reg4  <= Intra_mbAddrA_Cr_reg4;
						Intra_mbAddrA_reg5  <= Intra_mbAddrA_Cr_reg5;
						Intra_mbAddrA_reg6  <= Intra_mbAddrA_Cr_reg6;
						Intra_mbAddrA_reg7  <= Intra_mbAddrA_Cr_reg7;
						Intra_mbAddrA_reg8  <= 0;	Intra_mbAddrA_reg9  <= 0;
						Intra_mbAddrA_reg10 <= 0;	Intra_mbAddrA_reg11 <= 0;
						Intra_mbAddrA_reg12 <= 0;	Intra_mbAddrA_reg13 <= 0;
						Intra_mbAddrA_reg14 <= 0;	Intra_mbAddrA_reg15 <= 0;
					end
				else
					begin
						Intra_mbAddrA_reg0  <= 0;	Intra_mbAddrA_reg1  <= 0;
						Intra_mbAddrA_reg2  <= 0;	Intra_mbAddrA_reg3  <= 0;
						Intra_mbAddrA_reg4  <= 0;	Intra_mbAddrA_reg5  <= 0;
						Intra_mbAddrA_reg6  <= 0;	Intra_mbAddrA_reg7  <= 0;
						Intra_mbAddrA_reg8  <= 0;	Intra_mbAddrA_reg9  <= 0;
						Intra_mbAddrA_reg10 <= 0;	Intra_mbAddrA_reg11 <= 0;
						Intra_mbAddrA_reg12 <= 0;	Intra_mbAddrA_reg13 <= 0;
						Intra_mbAddrA_reg14 <= 0;	Intra_mbAddrA_reg15 <= 0;
					end
			end
		else
			begin
				Intra_mbAddrA_reg0  <= 0;	Intra_mbAddrA_reg1  <= 0;
				Intra_mbAddrA_reg2  <= 0;	Intra_mbAddrA_reg3  <= 0;
				Intra_mbAddrA_reg4  <= 0;	Intra_mbAddrA_reg5  <= 0;
				Intra_mbAddrA_reg6  <= 0;	Intra_mbAddrA_reg7  <= 0;
				Intra_mbAddrA_reg8  <= 0;	Intra_mbAddrA_reg9  <= 0;
				Intra_mbAddrA_reg10 <= 0;	Intra_mbAddrA_reg11 <= 0;
				Intra_mbAddrA_reg12 <= 0;	Intra_mbAddrA_reg13 <= 0;
				Intra_mbAddrA_reg14 <= 0;	Intra_mbAddrA_reg15 <= 0;
			end	
	//Intra_mbAddrA_window0 ~ 3
	always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode
		or blk4x4_intra_calculate_counter or blk4x4_rec_counter or mbAddrA_availability	
		
		or Intra_mbAddrA_reg0  or Intra_mbAddrA_reg1  or Intra_mbAddrA_reg2  or Intra_mbAddrA_reg3  
		or Intra_mbAddrA_reg4  or Intra_mbAddrA_reg5  or Intra_mbAddrA_reg6  or Intra_mbAddrA_reg7  
		or Intra_mbAddrA_reg8  or Intra_mbAddrA_reg9  or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11
		or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15
		
		or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2 or Intra_mbAddrA_Cb_reg3
		or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5 or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7
		or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2 or Intra_mbAddrA_Cr_reg3
		or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5 or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7)
		if (mb_type_general[3] == 1'b1)
			begin
				//Intra4x4 && Intra16x16_horizontal
				if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 && 
					(mb_type_general[2] == 1'b1 || (
					(mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Horizontal))))
					case (blk4x4_rec_counter)
						0,1,4,5:
						begin
							Intra_mbAddrA_window0 <= Intra_mbAddrA_reg0; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg1;
							Intra_mbAddrA_window2 <= Intra_mbAddrA_reg2; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg3;
						end
						2,3,6,7:
						begin
							Intra_mbAddrA_window0 <= Intra_mbAddrA_reg4; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg5;
							Intra_mbAddrA_window2 <= Intra_mbAddrA_reg6; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg7;
						end
						8,9,12,13:
						begin
							Intra_mbAddrA_window0 <= Intra_mbAddrA_reg8; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg9;
							Intra_mbAddrA_window2 <= Intra_mbAddrA_reg10;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg11;
						end
						10,11,14,15:
						begin
							Intra_mbAddrA_window0 <= Intra_mbAddrA_reg12;Intra_mbAddrA_window1 <= Intra_mbAddrA_reg13;
							Intra_mbAddrA_window2 <= Intra_mbAddrA_reg14;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg15;
						end
						default:
						begin