intra_pred_pe.v

a H.264/AVC Baseline Decoder

//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : [e-mail]
// File      : Intra_pred_PE.v
// Generated : Sep 19, 2005
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Processing Element for Intra prediction,PE0 ~ PE3
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module Intra_pred_PE (clk,reset_n,mb_type_general,blk4x4_rec_counter,blk4x4_intra_calculate_counter,
	Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode,
	blkAddrA_availability,blkAddrB_availability,mbAddrA_availability,mbAddrB_availability, 
	
	Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3,
	Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3,
	Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3,
	Intra_mbAddrD_window,
	
	Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3,
	Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7,
	Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11,
	Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15,
	Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3,
	Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7,
	Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11,
	Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15,
	
	blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2,
	blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6,
	blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,
	blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,
	
	seed,b,c,
	
	PE0_out,PE1_out,PE2_out,PE3_out,PE0_sum_out,PE3_sum_out);
	input clk,reset_n;
	input [3:0] mb_type_general;
	input [4:0] blk4x4_rec_counter;
	input [2:0] blk4x4_intra_calculate_counter;
	input [3:0]	Intra4x4_predmode;
	input [1:0] Intra16x16_predmode;
	input [1:0] Intra_chroma_predmode;
	input blkAddrA_availability;
	input blkAddrB_availability;
	input mbAddrA_availability;
	input mbAddrB_availability;
	input [15:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
	input [15:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
	input [15:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
	input [15:0] Intra_mbAddrD_window;
	input [15:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
	input [15:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
	input [15:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
	input [15:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
	input [15:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
	input [15:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
	input [15:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
	input [15:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
	input [15:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2;
	input [15:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6;
	input [15:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10;
	input [15:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14;
	input [15:0] seed;
	input [11:0] b,c;
	
	output [7:0] PE0_out;
	output [7:0] PE1_out;
	output [7:0] PE2_out;
	output [7:0] PE3_out;
	output [15:0] PE0_sum_out; //for store as 2nd-level seed
	output [15:0] PE3_sum_out;	//for store as 2nd-level seed
	
	reg [15:0] PE0_in0,PE0_in1,PE0_in2,PE0_in3;
	reg PE0_IsShift;
	reg PE0_IsStore;
	reg PE0_IsClip;
	reg PE0_full_bypass;
	reg [4:0] PE0_round_value;
	reg [2:0] PE0_shift_len;
	
	reg [15:0] PE1_in0,PE1_in1,PE1_in2,PE1_in3;
	reg PE1_IsShift;
	reg PE1_IsStore;
	reg PE1_IsClip;
	reg PE1_full_bypass;
	reg [4:0] PE1_round_value;
	reg [2:0] PE1_shift_len; 
	
	reg [15:0] PE2_in0,PE2_in1,PE2_in2,PE2_in3;
	reg PE2_IsShift;
	reg PE2_IsStore;
	reg PE2_IsClip;
	reg PE2_full_bypass;
	reg [4:0] PE2_round_value;
	reg [2:0] PE2_shift_len; 
	
	reg [15:0] PE3_in0,PE3_in1,PE3_in2,PE3_in3;
	reg PE3_IsShift;
	reg PE3_IsStore;
	reg PE3_IsClip;
	reg PE3_full_bypass;
	reg [4:0] PE3_round_value;
	reg [2:0] PE3_shift_len;
	
	wire [15:0] PE0_out_reg;
	wire [15:0] PE1_out_reg;
	wire [15:0] PE2_out_reg;
	wire [15:0] PE3_out_reg;
	
	wire [15:0] PE0_sum_out;
	wire [15:0] PE1_sum_out;
	wire [15:0] PE2_sum_out;
	wire [15:0] PE3_sum_out;
	
	wire [15:0] b_ext,c_ext;
	assign b_ext = (b[11] == 1'b1)? {4'b1111,b}:{4'b0000,b};
	assign c_ext = (c[11] == 1'b1)? {4'b1111,c}:{4'b0000,c};
	
	PE PE0	(
		.clk(clk),
		.reset_n(reset_n),
		.in0(PE0_in0),
		.in1(PE0_in1),
		.in2(PE0_in2),
		.in3(PE0_in3),
		.IsShift(PE0_IsShift),
		.IsStore(PE0_IsStore),
		.IsClip(PE0_IsClip),
		.full_bypass(PE0_full_bypass),
		.round_value(PE0_round_value),
		.shift_len(PE0_shift_len),
		.PE_out_reg(PE0_out_reg),
		.PE_out(PE0_out),
		.sum_out(PE0_sum_out)
		);
	PE PE1	(
		.clk(clk),
		.reset_n(reset_n),
		.in0(PE1_in0),
		.in1(PE1_in1),
		.in2(PE1_in2),
		.in3(PE1_in3),
		.IsShift(PE1_IsShift),
		.IsStore(PE1_IsStore),
		.IsClip(PE1_IsClip),
		.full_bypass(PE1_full_bypass),
		.round_value(PE1_round_value),
		.shift_len(PE1_shift_len),
		.PE_out_reg(PE1_out_reg),
		.PE_out(PE1_out),
		.sum_out(PE1_sum_out)
		);
	PE PE2	(
		.clk(clk),
		.reset_n(reset_n),
		.in0(PE2_in0),
		.in1(PE2_in1),
		.in2(PE2_in2),
		.in3(PE2_in3),
		.IsShift(PE2_IsShift),
		.IsStore(PE2_IsStore),
		.IsClip(PE2_IsClip),
		.full_bypass(PE2_full_bypass),
		.round_value(PE2_round_value),
		.shift_len(PE2_shift_len),
		.PE_out_reg(PE2_out_reg),
		.PE_out(PE2_out),
		.sum_out(PE2_sum_out)
		);
	PE PE3	(
		.clk(clk),
		.reset_n(reset_n),
		.in0(PE3_in0),
		.in1(PE3_in1),
		.in2(PE3_in2),
		.in3(PE3_in3),
		.IsShift(PE3_IsShift),
		.IsStore(PE3_IsStore),
		.IsClip(PE3_IsClip),
		.full_bypass(PE3_full_bypass),
		.round_value(PE3_round_value),
		.shift_len(PE3_shift_len),
		.PE_out_reg(PE3_out_reg),
		.PE_out(PE3_out),
		.sum_out(PE3_sum_out)
		);
	//----
	//PE0 |
	//----
	always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter
		or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode
		or blkAddrA_availability or blkAddrB_availability or mbAddrA_availability or mbAddrB_availability
		or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2
		or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3
		or Intra_mbAddrD_window
		or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3
		or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2 or Intra_mbAddrB_reg3
		or PE0_out_reg or PE1_out_reg or PE2_out_reg or PE3_out_reg
		or blk4x4_pred_output4 or blk4x4_pred_output5  or blk4x4_pred_output8
		or blk4x4_pred_output9 or blk4x4_pred_output10 or blk4x4_pred_output12
		or seed or b_ext or c_ext)
		//Intra 4x4
		if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
			case (Intra4x4_predmode)
				`Intra4x4_Vertical:	
				begin
					case (blk4x4_intra_calculate_counter)
						4:PE0_in0 <= Intra_mbAddrB_window0;
						3:PE0_in0 <= Intra_mbAddrB_window1;
						2:PE0_in0 <= Intra_mbAddrB_window2;
						1:PE0_in0 <= Intra_mbAddrB_window3;
						default:PE0_in0 <= 0;
					endcase
					PE0_in1 	    <= 0; 	PE0_in2    	    <= 0;	PE0_in3 	  <= 0;	
					PE0_IsShift     <= 0;	PE0_IsStore     <= 0;	PE0_IsClip    <= 0;	
					PE0_full_bypass <= 1;	PE0_round_value <= 0;	PE0_shift_len <= 0;
				end
				`Intra4x4_Horizontal:
				begin
					PE0_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window0:0;
					PE0_in1 	    <= 0; 	PE0_in2 		<= 0;	PE0_in3       <= 0; 	
					PE0_IsShift     <= 0;	PE0_IsStore     <= 0;	PE0_IsClip    <= 0;
					PE0_full_bypass <= 1;	PE0_round_value <= 0;	PE0_shift_len <= 0;
				end
				`Intra4x4_DC:
				case (blk4x4_intra_calculate_counter)
					4:		//A ~ D
					begin
						if (blkAddrB_availability == 1)
							begin
								PE0_in0 <= Intra_mbAddrB_window0;	PE0_in1 <= Intra_mbAddrB_window1;
								PE0_in2 <= Intra_mbAddrB_window2;	PE0_in3 <= Intra_mbAddrB_window3;
								PE0_IsStore <= 1'b1;				PE0_full_bypass <= 1'b0;
							end
						else
							begin
								PE0_in0 <= 0;	PE0_in1 <= 0;	PE0_in2 <= 0;	PE0_in3 <= 0;
								PE0_IsStore <= 1'b0;			PE0_full_bypass <= 1'b1;
							end
						PE0_IsShift     <= 0;	PE0_IsClip    <= 0;
						PE0_round_value <= 0;	PE0_shift_len <= 0;
					end
					3:
					begin
						case ({blkAddrB_availability,blkAddrA_availability})
							2'b00:
							begin
								PE0_in0 <= 128;				PE0_in1 <= 0;	
								PE0_full_bypass <= 1'b1;	PE0_round_value <= 0;	PE0_shift_len <= 0;
							end
							2'b01,2'b10:
							begin
								PE0_in0 <= (blkAddrB_availability)? PE0_out_reg:0;
								PE0_in1 <= (blkAddrA_availability)? PE1_out_reg:0;
								PE0_full_bypass <= 1'b0;	PE0_round_value <= 2;	PE0_shift_len <= 2;
							end
							2'b11:
							begin
								PE0_in0 <= PE0_out_reg;	PE0_in1 <= PE1_out_reg;
								PE0_full_bypass <= 1'b0;	PE0_round_value <= 4;	PE0_shift_len <= 3;
							end
						endcase
						PE0_in2 <= 0;		PE0_in3 <= 0;
						PE0_IsStore <= 0;	PE0_IsShift <= 0;	PE0_IsClip <= 0;
					end
					default:
					begin
						PE0_in0 <= 0;	PE0_in1 <= 0;	PE0_in2 <= 0;	PE0_in3 <= 0; 		
						PE0_IsShift <= 0;		PE0_IsStore <= 0;	PE0_IsClip <= 0;	
						PE0_full_bypass <= 1;	PE0_round_value <= 0;	PE0_shift_len <= 0;
					end
				endcase
				`Intra4x4_Diagonal_Down_Left:
				begin
					case (blk4x4_intra_calculate_counter)
						4:PE0_in0 <= Intra_mbAddrB_window0;
						3:PE0_in0 <= blk4x4_pred_output4;
						2:PE0_in0 <= blk4x4_pred_output8;
						1:PE0_in0 <= blk4x4_pred_output12;
						default:PE0_in0 <= 0;
					endcase
					PE0_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window2:0;
					PE0_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0;
					PE0_in3 <= 0;
					PE0_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0;
					PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0;
					PE0_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1;
					PE0_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'b00010:5'b0; // +2
					PE0_shift_len	<= (blk4x4_intra_calculate_counter == 4)? 3'b010:3'b0;   // >>2
				end