intra_pred_pipeline.v

a H.264/AVC Baseline Decoder

					plane_HV_mux1_sel <= 1'b0;	plane_HV_mux2_sel <= 1'b0;
				end
				6,3:	//x2,x4
				begin
					plane_HV_prev_in <= plane_HV_out_reg;	plane_HV_Is7 <= 1'b0;
					plane_HV_A1 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg5:Intra_mbAddrB_reg5;		
					plane_HV_A2 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg1:Intra_mbAddrB_reg1;
					plane_HV_B1 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg7:Intra_mbAddrB_reg7;	
					plane_HV_B2 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrD_window :Intra_mbAddrD_window;
					plane_HV_shifter1_len <= 2'b01; plane_HV_shifter2_len <= 2'b01;
					plane_HV_mux1_sel <= 1'b1;      plane_HV_mux2_sel <= 1'b1;
				end
				default:
				begin
					plane_HV_prev_in <= 0;	plane_HV_Is7 <= 0;
					plane_HV_A1 <= 0;	plane_HV_A2 <= 0;	plane_HV_B1 <= 0;	plane_HV_B2 <= 0;
					plane_HV_shifter1_len <= 0;	plane_HV_shifter2_len <= 0;
					plane_HV_mux1_sel <= 0;     plane_HV_mux2_sel <= 0;
				end
			endcase
		else
			begin
				plane_HV_prev_in <= 0;	plane_HV_Is7 <= 0;
				plane_HV_A1 <= 0;	plane_HV_A2 <= 0;	plane_HV_B1 <= 0;	plane_HV_B2 <= 0;
				plane_HV_shifter1_len <= 0;	plane_HV_shifter2_len <= 0;
				plane_HV_mux1_sel <= 0;     plane_HV_mux2_sel <= 0;
			end
			
	wire Is_HV_latch;
	assign Is_HV_latch = ((blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter != 7 && blk4x4_intra_precompute_counter != 2 && 
		blk4x4_intra_precompute_counter != 1 && blk4x4_intra_precompute_counter != 0) || (
		(blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && (blk4x4_intra_precompute_counter != 5 && 
		blk4x4_intra_precompute_counter != 2 && blk4x4_intra_precompute_counter != 1 && blk4x4_intra_precompute_counter != 0)));
	always @ (posedge clk)
		if (reset_n == 1'b0)
			plane_HV_out_reg <= 0;
		else if (Is_HV_latch)
			plane_HV_out_reg <= plane_HV_out;
	
	//	2.2 precomputation for b,c
	reg [14:0] plane_bc_in;
	reg plane_bc_IsLuma;
	wire [11:0] plane_bc;
	plane_bc_precomputation plane_bc_precomputation (
		.HV_in(plane_bc_in),
		.IsLuma(plane_bc_IsLuma),
		.bc_out(plane_bc)
		);
	always @ (mb_type_general[3:2] or Intra16x16_predmode or blk4x4_rec_counter or blk4x4_intra_precompute_counter or plane_HV_out_reg)
		//Intra16x16 plane
		if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_rec_counter == 0)
			case (blk4x4_intra_precompute_counter)
				7,2    :begin	plane_bc_in <= plane_HV_out_reg;	plane_bc_IsLuma <= 1'b1;	end
				default:begin	plane_bc_in <= 0;                 plane_bc_IsLuma <= 1'b0;	end
			endcase
		//Chroma Cb,Cr plane
		else if (mb_type_general[3] == 1'b1 && (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20))
			case (blk4x4_intra_precompute_counter)
				5,2    :begin	plane_bc_in <= plane_HV_out_reg; plane_bc_IsLuma <= 1'b0;	end
				default:begin	plane_bc_in <= 0;                plane_bc_IsLuma <= 1'b0;	end
			endcase
		else
			begin	plane_bc_in <= 0;					plane_bc_IsLuma <= 1'b0;	end
	
	wire c_latch_ena;
	assign c_latch_ena = ((blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter == 7) || 
		((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_precompute_counter == 5));
	always @ (posedge clk)
		if (reset_n == 0)
			plane_c_reg <= 0;
		else if (c_latch_ena) 
			plane_c_reg <= plane_bc;
	//	2.3 precomputation for a,and latch a & b at the same time at cycle 2
	reg [7:0] plane_a_pix_in1,plane_a_pix_in2;
	wire [13:0] plane_a;
	reg [13:0] plane_a_reg;
	
	plane_a_precomputation plane_a_precomputation(
	.pix_in1(plane_a_pix_in1),
	.pix_in2(plane_a_pix_in2),
	.a_out(plane_a)
	);
	always @ (blk4x4_rec_counter or blk4x4_intra_precompute_counter or Intra_mbAddrA_reg15 
		or Intra_mbAddrB_reg15 or Intra_mbAddrA_reg7 or Intra_mbAddrB_reg7)
		//Intra16x16
		if (blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter == 2)
			begin	
				plane_a_pix_in1 <= Intra_mbAddrA_reg15;	
				plane_a_pix_in2 <= Intra_mbAddrB_reg15;	
			end
		//Chroma 
		else if((blk4x4_rec_counter == 16  || blk4x4_rec_counter == 20) && blk4x4_intra_precompute_counter == 2)
			begin
				plane_a_pix_in1 <= Intra_mbAddrA_reg7;	
				plane_a_pix_in2 <= Intra_mbAddrB_reg7;	
			end
		else
			begin
				plane_a_pix_in1 <= 0;
				plane_a_pix_in2 <= 0;
			end	
			
	wire ab_latch_ena;
	assign ab_latch_ena = (blk4x4_intra_precompute_counter == 2);
	always @ (posedge clk)
		if (reset_n == 1'b0)
			begin
				plane_a_reg <= 0;
				plane_b_reg <= 0;
			end
		else if (ab_latch_ena)
			begin
				plane_a_reg <= plane_a;
				plane_b_reg <= plane_bc;
			end
	//	2.4 precomputation for main seed @ blk4x4_intra_precompute_counter == 1
	wire [13:0] main_seed_a;
	wire [11:0] main_seed_b,main_seed_c;
	wire main_seed_IsIntra16x16;
	
	main_seed_precomputation main_seed_precomputation (
		.a(main_seed_a),
		.b(main_seed_b),
		.c(main_seed_c),
		.IsIntra16x16(main_seed_IsIntra16x16),
		.main_seed(main_seed)
		); 
	assign main_seed_a = (blk4x4_intra_precompute_counter == 1)? plane_a_reg:0;
	assign main_seed_b = (blk4x4_intra_precompute_counter == 1)? plane_b_reg:0;
	assign main_seed_c = (blk4x4_intra_precompute_counter == 1)? plane_c_reg:0;
	assign main_seed_IsIntra16x16 = (blk4x4_intra_precompute_counter == 1)? ((blk4x4_rec_counter == 0)? 1'b1:1'b0):1'b0;
	 
	//----------------------------------------------------------------------------------------	
	//3.calculation: by Intra_pred_PE.v 
	//----------------------------------------------------------------------------------------
	
endmodule

module plane_a_precomputation (pix_in1,pix_in2,a_out);
	input [7:0] pix_in1,pix_in2;
	output [13:0] a_out;
	
	wire [8:0] sum;
	assign sum = pix_in1 + pix_in2;
	assign a_out = {1'b0,sum,4'b0};
endmodule

module plane_bc_precomputation (HV_in,IsLuma,bc_out);
	input [14:0] HV_in;
	input IsLuma;
	output [11:0] bc_out;
	
	wire [16:0] multiply_4or16;
	wire [16:0] product;
	wire [5:0] addend;
	wire [16:0] sum;
	
	assign multiply_4or16 = (IsLuma)? {HV_in,2'b0}:{HV_in[12:0],4'b0};
	assign product = multiply_4or16 + {{2{HV_in[14]}},HV_in};
	assign addend = (IsLuma)? 6'b100000:6'b010000;	//32 for luma,16 for chroma
	assign sum = product + addend;
	assign bc_out = (IsLuma)? {sum[16],sum[16:6]}:sum[16:5];  
	
endmodule

module plane_HV_precomputation (prev_in,A1,A2,B1,B2,shifter1_len,shifter2_len,mux1_sel,mux2_sel,Is7,HV_out);
	input [14:0] prev_in;
	input [7:0] A1,A2,B1,B2;
	input [1:0] shifter1_len,shifter2_len;
	input mux1_sel,mux2_sel;
	input Is7;
	output [14:0] HV_out;
	
	wire [7:0] neg_A2;
	wire signed [8:0] A1_minus_A2;
	wire signed [11:0] shifter1_out;
	wire [11:0] mux1_out;
	wire [14:0] adder1_out;
	wire [7:0] neg_B2;
	wire signed [8:0] B1_minus_B2;
	wire signed [11:0] shifter2_out;
	wire [9:0] mux2_out;
	wire [9:0] neg_mux2_out;
	wire [11:0] adder2_out;
	//Left part,multiply by 1,2,4,8
	assign neg_A2 = ~A2;
	assign A1_minus_A2 = {1'b0,A1} + {1'b1,neg_A2} + 1;	
	assign shifter1_out = A1_minus_A2 <<< shifter1_len;
	assign mux1_out = (mux1_sel == 1'b0)? {{3{A1_minus_A2[8]}},A1_minus_A2}:shifter1_out;
	assign adder1_out = prev_in + {{3{mux1_out[11]}},mux1_out};
	//Right part,multiply by 3,5,6,7
	assign neg_B2 = ~B2;
	assign B1_minus_B2 = {1'b0,B1} + {1'b1,neg_B2} + 1;
	assign shifter2_out = B1_minus_B2 <<< shifter2_len;
	assign mux2_out = (mux2_sel == 1'b0)? {B1_minus_B2[8],B1_minus_B2}:{B1_minus_B2,1'b0};
	assign neg_mux2_out = (Is7 == 1'b1)? (~mux2_out + 1):mux2_out;
	assign adder2_out = shifter2_out + {{2{neg_mux2_out[9]}},neg_mux2_out};
	assign HV_out = adder1_out + {{3{adder2_out[11]}},adder2_out};
endmodule

module main_seed_precomputation (a,b,c,IsIntra16x16,main_seed);
	input [13:0] a;
	input [11:0] b,c;
	input IsIntra16x16;
	output [15:0] main_seed;
	
	wire [14:0]	b_x8_or_x4;
	wire [14:0] c_x8_or_x4;
	wire [11:0] neg_b;
	wire [14:0] b_x7_or_x3;
	wire [15:0] neg_b_x7_or_x3;
	wire [15:0] neg_c_x8_or_x4;
		
	assign b_x8_or_x4 = (IsIntra16x16)? {b[11:0],3'b0}:{b[11],b[11:0],2'b0};
	assign c_x8_or_x4 = (IsIntra16x16)? {c[11:0],3'b0}:{c[11],c[11:0],2'b0};
	assign neg_b = ~ b;
	assign b_x7_or_x3 = b_x8_or_x4 + {{3{neg_b[11]}},neg_b} + 1;
	assign neg_b_x7_or_x3 = {~b_x7_or_x3[14],~b_x7_or_x3} + 1;
	assign neg_c_x8_or_x4 = {~c_x8_or_x4[14],~c_x8_or_x4} + 1;
	assign main_seed = {a[13],a[13],a} + (neg_c_x8_or_x4 + neg_b_x7_or_x3);
endmodule